Facit 4431, Service Instruction

Page 1: ...LIST OF CONTENT AT PAGES 42 43 SERVICE INSTRUCTION 4431 Edition 1 Pub1 No 1160 82 17 12 8 Eng DECEMBER 1982 K F Printed in Sweden VIDEO TERMINAL __ Facit AB Technical Service Department S 59700 ATVIDA...

Page 2: ...Random Access Memory Read Only Memory Serial Input output or Dual channel Asynchronous Receiver Transmitter 1 1 DESIGN The terminal consists of three major physical subassemblies the Main Logic Board...

Page 3: ...led cable The V24 RS232C sig nal cables are provided by the customer 2 2 POWER ON PERFORMANCE CHECK Inspection before power on check that the model plate corresponds to order and packing case marking...

Page 4: ...o 75 by depressing of key 7 and 8 Recall fac tory settings by depressing the Shift key and R at the same time SHIFT R Return to SET UP B mode f depress key 5 to enter SET UPC mode Make the same proced...

Page 5: ...TO KEYBOARD PCB The user will need access to the keyboard p c b to allow the setting of jumpers described in sections and access is gained as follows Switch off the unit and disconnect the key board...

Page 6: ...ard is for use in Jumper W3 is not fitted The table below shows the possible combinations The keyboard will be supplied set to one particular configu ration with appropriate keytops fitted If a change...

Page 7: ...d pins 7 3 5 2 3 Production Test W4 This jumper is used only during production It must not be fitted during normal operation 3 5 2 4 Disable Enable Save W5 The user may prevent the operator saving alt...

Page 8: ...acit 4431 The terminal connectors may be internally linked via jumper to provide a 5V supply to the adapter which is all that is required for passive passive operation Where the user wishes to employ...

Page 9: ...nge Tabs Clear All Tabs 80 132 Column Page 1 Page 2 Set up B 2 to toggle 3 9 to toggle PF1 I PF2 80 column 2 page mode 5 Set PF Keys sequence Set Answerback message T0ggle displayed switches SHIFT PFx...

Page 10: ...other real time functions The microprocessor controls all communication on the CPU bus reading data from the EPROMS EAROM display refresh RAM SIO and the keyboard and writing to the dis play refresh R...

Page 11: ...data is controlled by the DISPLAY ACCESS HANDLER circuitry A block diagram of the Display Refresh Memory is shown in Fig 6 2 TO VG 18 TO VG 1 4 4 _ DISPLAY MEMORY ASCII BUFFERS D54 55 ATTR BUFFER D70...

Page 12: ...it uses the outputs of the Sync generator and the display memory circuits to create the appropriate video sig nals for each character to be displayed The ASCII character code from the display memory t...

Page 13: ...S 061 RS232C i TO TTL i _ LINE RECEIVERS 14 062 __ __ I O SER OUT I O DTR I O RTS I O SER IN I O DSR I O CTS I O PORT P SER OUT PRINTER P SER IN PORT P ROY INT REQUEST FIG 6 5 INPUT OUTPUT PRINTER INT...

Page 14: ...e section 7 5 the EAROM D63 various hardware latches and under control of the bus arbitration circuitry the display refresh RAM 051 52 and the attri bute RAM D68 69 67 and D66 Address decoding for all...

Page 15: ...ROM 15 the CPU must suspend all other operations while generating the clock data and control signals To insure that non maskable interrupts are dis abled the CPU latches a high to D64 2 for the durati...

Page 16: ...active state At the start of the pro cessor portion of the character time cycle the rising edge of the MEMSHARE signal will switch the display RAM address multiplexers D27 D10 and D13 over to the CPU...

Page 17: ...esh memory is accessed in a transparent manner This requires that one half of the character time be devoted to CPU access and the other half to the refresh me mory circuitry To synchronize the various...

Page 18: ...v JI P A _L I ar _ i A I IV J r I I f i wl _ I _ 0 J l J J r A WQ A 10 i t r r i l 10 i t t t r t o i _ __ _ _ __ __ _ 80 column mode 132 column mode VERT 2V cm HORIZ 100ns cm FIG 7 2 DOT OSCILLATOR...

Page 19: ...ooth scroll this will always be zero The new row start address is written during the horizontal blanking period which guarantees that the screen will not be disturbed When the processor under software...

Page 20: ...al sync pulse must always be allowed to generate NMI the vertical sync pulse presets F F D3 As interrupts from the scan line counter would normally occur at the very beginning of a scan line the proce...

Page 21: ...nerator is al ways looking up the data for the next character to be displayed i e it is always one charac ter ahead of the video beam and the display RAM is accesing data for the second character to b...

Page 22: ...to allow the double high characters to be formed The outputs of 021 go to the address inputs A1 A2 A4 and A8 of 019 the 74LS288 bipolar ROM The A16 input 019 14 can be considered as the double high i...

Page 23: ...tical and horizontal blan king is buffered through 046 and then through 035 The blank output at 02 11 is ANDed 037 1 2 with the LSB data out of the character genera tor This data bit DO is the extensi...

Page 24: ...ts stop bits parity word lenght etc from the Set Up mode soft switches and programs the DART for these characteristics The DART then takes care of all parallel serial data con version and data formati...

Page 25: ...or is faulty 9 1 1 POWER UP SELF TEST Upon Power Up the 4431 tests the program EPROM s EAROM processor scratchpad RAM and the display refresh memory If the terminal halts with the LEDs on then the pro...

Page 26: ...the serial 1 0 lines are faulty The bell will ring twice to signify the start of the Keyboard Test Mode The tech nician will then type the following twelve character sequence XB G L Return 0 KLINE FEE...

Page 27: ...r supply and the ten pin connector from the Main Logic and remove the CRT assembly by tilting it back and lifting it up carefully The above operation should be reversed to in stall the replacement mon...

Page 28: ...ntiometer CW and CCW so that the display folds over the margins note these positions and adjust the potentiometer half way between these points e BRIGHTNESS CONTROL SET UP A mode First reset the termi...

Page 29: ...oes not blink ___ ________ Check D50 D42 D72 Ch ck interrupt priority chain No video but Be11 works _______ D57 bad screen blank Bad CRT Missing dots in characters_____ Bad Chr Gen D15 Bad D39 or D38...

Page 30: ...3 J LI R 057 Fl R1 J V103 R21 R18 Iv _C2 X6 I I I I B R20 U 12 R29 O Q Q U RX I 1 I I I I I o IVv102 I C35 I I tg Q I 048 ck I I j Q I J 049 I C32 I CJ 050 D I C39 I o 61 062 063 V107 065 I 040 J 051...

Page 31: ...f 1G3 F4 AJS 2 j G2 F 4 G3 F4 I___ _ II Al 2 3 13_ Pi2 DO DI IS D2 D3 17 D4 DS g Al 23 d _ DO t t DI t t IS D2 t t D3 1 ihlI_ D4 t 10 DS D6 t D7 ll l 11 RESET CLK MPQ MRQ 13 Ghf D24 Al4 Dl4 Di6 9 8 AJ...

Page 32: ...MAS A256 MA9 1L A512 _ 1 a2Cl G3 F5 F4 __ ______ _ l 0 2Cl G3 F5 2 F4 r A 2 3 415 ATO 1 A ID 13 ll 12 ATl 1 lk JL_ AT2 L____ Jl l AT3 A 2 3 4 5 ATO 1 A 1 ID 13 1 11 12 AT 1 1 1 11 AT2 AT3 DG7 MA0 I 1...

Page 33: ...r1L AG A I I L II n 9 IO iA v L t MA7 MEM 2CT l5 i lL A7 A I 2 D7 3 4 1 6 1 04 2 1 7 NMI CPU 5 D20 Dl2 0 15 Dl3 13 II 9 2 c 1 2 3 lfC4 1 1 5 tAI 5V c7 tGI G2 1 05 0 2 0 HSYNC O 12 Dl7 2 1 II D30 5 1 l...

Page 34: ...5 t DM7 MEMl 3 IJU I 2 1 t t t SI 2 _ __ _ At 24 5 A I 7 6 A 0 2 llA I 2 s2 10 A 0 S 3 14 A J 2 12 S4 13 A 0 S5 A 1 12V 5V 0 I iil t 4 tPVJ02 6 RJL Rl4 5 060 1 2k 90 _____ t i J 5 058 ______ l i6 S3...

Page 35: ...Ir D7 CE A3 5V li i I 8 SJ 5 1 6 D47 D45 UART DO 10l3A 4 1 3 DI so D2 SI 20 D45 03 PE D4 FE D5 OR I DG cs y D7 NP y DO TSB 1 M DI NB2 D2 NBI tM D3 EPS 17 if D4 RXC Io 5V ft D5 TXC D6 SWE 16 D7 XR RI 1...

Page 36: ...8 A256 A512 Al024 2 3Cl G4 F5 G2 F5 G3 5V DO DI D2 D3 D4 D5 D6 D7 DO DI D2 D3 D4 D5 D6 D7 Bl B2 B3 B4 B5 B6 B7 B8 DO DO DI D2 D3 D4 D5 D6 5 D7 r 0 a a U5 Al A2 A3 A4 A5 A6 A7 A8 A9 Al 0 All Al2 c AO A...

Page 37: ...1 2131410 o o o o o ojs 617 81 13 I 14 I 15 I 16 I 17 I 18 I 19 I 20 I 21 I 22 I 23 I 24 I 25 I 26 I 27 28 29 30 31 35 I 36 I 3 7 I 38 I 39 I 40 I 41 I 42 I 43 I 44 I 45 I 46 I 4 7 I 48 49 50 51 52 Ml...

Page 38: ...470p 6R4 270K 6P2 100K Amplitude SR2 6KB YJ re SR3 10K ri sea 1 I I see 100n HORIZONTAL 12 J OA9 _nSR14 1on 112w 5 IC TOA 1180 P 6C22 6R16 I 22 82K VERT rn YOKE I 5C212 5R208 220K 6R14 33K I 5R210 82...

Page 39: ...CIRCUIT BOARD 39 SL200 IS0208 SR 204 SR 206 SD 2101 SC 212 I S0206 I SL 206 SL 203 SC208 6R30 6R28 SC200 SR202 SC206 SC201 S0204 SC 204 SR201 L 0 l 6R24 6R26 6R20 6C18 604J 0 SR200 ST 200 aJ S02001 I...

Page 40: ...34 100p OT2 2N3055 locJa I OC52 33 25V I100 16V OR28 56fl 5V 2A5 17V OA3 12V OA3 12V OA9 c J T T 23V 10mA _O_i _6_ OZ2 ZPD22 OC24 12V OAI OC56 QOR32 4n7 OC54 I XJO 1 2k I 220 16V 16 v CHASS SIGNAL OR3...

Page 41: ...261 OC6 10028 0024 I a 0R14 0021 0R2 OR4 QRlD _JN I _0061 1 s OR 24 OC 2DI OR1t73 D04 0T1 OC14 DC16 DC62 cs c E I QC 22 I DC 36 OC42 QC 4D u 0 I 1 00101 OR6 0 OR3D C OL4 I QI I I i lD018 OR28 C 01 20...

Page 42: ...ator W3 _______ 7 Production Test W4 I Disable Enable Save W5 I NT E R F A C E I NF 0 R MAT I 0 N 8 V 24 RS 232 C COMMUNICATION INTERFACE V 24 RS 232 C PRINTER INTERFACE CURRENT LOOP INTERFACE COMPOSI...

Page 43: ...video output I INPUT OUTPUT INTERFACES 24 BAUD RATE CLOCK GENERATION DART OPERATIONS KEYBOARD COMMUNICATION M0 N I T 0 R A ND P 0 WE R S UP P L Y GENERAL MONITOR POWER SUPPLY_________________ 25 S E R...

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