Fujitsu CPU369-Module Documentation Download | Manualshive

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CPU369-Module

Documentation

©

Fujitsu Microelectronics Europe GmbH

Am Siebenstein 6-10

63303 Dreieich-Buchschlag, Germany

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Summary of Contents for CPU369-Module

Page 1: ...CPU369 Module Documentation Fujitsu Microelectronics Europe GmbH Am Siebenstein 6 10 63303 Dreieich Buchschlag Germany ...

Page 2: ...History Revision Date Comment V1 0 08 03 01 New Document V1 1 17 10 03 Modifications for F369 module V1 2 14 11 03 Some corrections 2 ...

Page 3: ...ect Fujitsu Microelectronics Europe GmbH entire liability and the customer s exclusive remedy shall be at Fujitsu Microelectronics Europe GmbH sole discretion either return of the purchase price and the license fee or replacement of the Product or parts thereof if the Product is returned to Fujitsu Microelectronics Europe GmbH in original packing and without further defects resulting from the cust...

Page 4: ...D ROM For documentation or software updates please refer to our technical web site http www fme gsdc de gsdc htm or to our Fujitsu home pagee http www fme fujitsu com Fujitsu reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice 4 ...

Page 5: ...e subboards just by plugging them to the CPU board The board allows the designer immediately to start the software development and perform debugging before his own final target system is available 2 Features MCU MB91F369 2MB external Debugging RAM 4MHz crystal DC Power supply circuit incl testpins for VCC GND power LED and switch 1 MB external Flash available for user code and constant data Extern...

Page 6: ...F Jumper setting Description ON closed Power supply 3V3 power supply JP11 OFF open NO Power supply Jumper setting Description ON closed Power supply 5V0 power supply JP12 OFF open NO Power supply Jumper setting Description ON closed Voltage regulator enable Bypass Capacitor Pin JP13 OFF open Voltage regulator disable Jumper setting Description ON closed Power supply Power supply for SMT JP14 OFF o...

Page 7: ...t enable SOT_0 JP21 OFF open UART0 Output disable Jumper setting Description ON closed UART0 Input enable SIN_0 JP22 OFF open UART0 Input disable Reserved future extension Description SIN_2 JP7 UART2 Input enable Description SOT_2 JP8 UART2 Output enable Description UART2 clock JP9 UART2 clock enable 3 4 Chip select enable for FLASH JP10 CS Jumper setting Description CS2 ON closed 1 2 Ext Flash Ch...

Page 8: ...2 3 32kHz clock disable Jumper setting Description 1 2 Low pass filter for clock enable Low pass filter JP20 2 3 Low pass filter for clock disable 3 7 CAN controller interface JP23 JP24 Jumper setting Description ON closed Transmit data enable CAN transmit JP23 OFF open Transmit data disable Jumper setting Description ON closed Receive data enable CAN receive JP24 OFF open Receive data disable 3 8...

Page 9: ...GO PM1 Sound Generator SGA BUS_PN5 0 Serial I O Interface signals SOT3 4 SIN3 4 SCK3 4 BUS_PO7 0 PPG output 7 0 PQ5 2 Serial I O Interface signals SOT1 2 SIN1 2 IMPORTANT NOTE Some of the Pins of Peripheral_1 and Peripheral_2 are not connected This is because the original CPU board was designed for the MCU MB91F362 and this MCU has some additional resources e g stepper motor drivers more ADC chann...

Page 10: ...AN8 10 PO0 OCPA0 11 PG1 AN9 11 PO1 OCPA1 12 PG2 12 PO2 OCPA2 13 PG3 13 PO3 OCPA3 14 PG4 14 PO4 OCPA4 15 PG5 15 PO5 OCPA5 16 PG6 16 PO6 OCPA6 17 PG7 17 PO7 OCPA7 18 PI3 ATGX 18 PP2 TX1 19 DA0 DA0 19 PP3 RX1 20 DA1 20 PP4 21 ALARM ALARM 21 PP5 22 PK4 INT4 22 PQ2 23 PK5 INT5 23 PQ3 24 PK6 INT6 24 PQ4 25 PK7 INT7 25 PQ5 26 PL0 26 PR0 27 PL1 27 PR1 28 PL2 28 PR2 29 PL3 29 PR3 30 PL4 30 PR4 31 PL5 31 PR...

Page 11: ...nector J1 The following figure shows the power connection jack J1 This connector is used to connect an external regulated DC power supply voltage 7 5V 12V DC to the evaluation board It is recommended to use 7 5V to keep the power dissipation to a minimum Otherwise an additional heat sink for the linear voltage regulator might be necessary Shield is connected to positive voltage supply Centre is co...

Page 12: ...5 Schematics and Drawings 12 ...

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