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White Paper 

Implementing MLC NAND Flash 
for Cost-Effective, High-Capacity 
Memory 

Written by: Raz Dan and Rochelle Singer 

JANUARY 2003 

91-SR-014-02-8L, REV 1.0 

Summary of Contents for Flash Memory

Page 1: ...White Paper Implementing MLC NAND Flash for Cost Effective High Capacity Memory Written by Raz Dan and Rochelle Singer JANUARY 2003 91 SR 014 02 8L REV 1 0...

Page 2: ...ther connected devices offer users more and more functionality and personalization options the storage requirements of these devices have become substantially greater For example 2 5G terminals now in...

Page 3: ...ir MLC NAND technology implements reliability performance and media management enhancements to perfect MLC NAND without the need for a full scale controller e g ATA or SCSI The combination of MLC NAND...

Page 4: ...ranges for VTh instead of just two The first implementation of MLC uses four voltage levels see Figure 2 Each state is mapped to one of four combinations of two bits Therefore the cell can store two b...

Page 5: ...impact on data reliability Detecting the voltage levels in an MLC flash cell is a more precise and complex task than in a Binary flash cell subject to a higher probability of error that can affect da...

Page 6: ...a page and erasing a flash unit Especially for write operations raw flash comparisons indicate that MLC performance is only 25 percent that of Binary flash But many factors other than raw flash speed...

Page 7: ...iles as compared with 172KBytes per second for MLC Note that the number of sectors per unit for MLC is twice the corresponding number for Binary flash When these figures are translated into percentage...

Page 8: ...algorithms performance enhancing innovations and flash management capabilities Developed in cooperation with Toshiba x2 technology is integrated seamlessly into the different modules of M Systems Mob...

Page 9: ...amlessly into M Systems TrueFFS It maps each virtual unit into a chain of physical units much in the same way that translation layers for Binary flash operate However unlike traditional translation la...

Page 10: ...re capable of correcting up to 4 errors per page using two industry standard error codes an extended Hamming code and a BCH Bose Chaudhuri and Hocquenghem code The Hamming code can detect 2 errors per...

Page 11: ...dia Without this capability a bad block in one plane would cause a good block in the second plane to be tagged as a bad block making it unusable This customized method of bad block handling for two pl...

Page 12: ...32 bit Transfer Data transfer from Flash Planes to FIFO Flash_OE Internal data transfers 16 bit Transfer 16 bit Transfer 16 bit Transfer 16 bit Transfer DiskOnChip_OE Data transfer from FIFO to Host...

Page 13: ...despite the additional benefits of MLC and x2 technology Summary The major improvements in flash NAND devices brought about by MLC technology are much smaller size per bit and consequently a greatly...

Page 14: ...nge without prior notice M Systems Flash Disk Pioneers Ltd assumes no responsibility for any errors that may appear in this document No part of this document may be reproduced transmitted transcribed...

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