Mesa 7I43, Manual

Page 1: ...7I43 7I43H MANUAL V3 0 ...

Page 2: ...This page intentionally not blank ...

Page 3: ... O CONNECTORS 6 JTAG CONNECTOR 8 POWER CONNECTOR 8 EPP INTERFACE CONNECTOR 9 OPERATION 10 FPGA 10 EPP CONFIGURATION 10 USB CONFIGURATION 11 EEPROM CONFIGURATION 12 EXTRA EEPROM SPACE 12 RECONFIGURATION 13 CONFIGURATION FILE STARTUP OPTIONS 13 SC7I43P and SC7I43W 13 CLOCK SIGNALS 14 EPP FPGA INTERFACE 14 USB FPGA INTERFACE 15 ADDITIONAL 7I43H INTERFACE PINS 16 LEDS 16 BUS SWITCH MODE 17 I O LEVELS ...

Page 4: ... 19 EPPIOPR8 19 USBIOPR8 20 LBP 21 EXAMPLE COMMANDS 22 LOCAL LBP COMMANDS 23 LOCAL LBP READ COMMANDS 23 LOCAL LBP WRITE COMMANDS 25 RPC COMMANDS 26 EXAMPLE RPC COMMAND LIST 27 AVAILABLE DAUGHTER CARDS 28 REFERENCE INFORMATION 29 SPECIFICATIONS 29 ...

Page 5: ...uposes as are 8 FPGA driven LEDs Several I O interface daughter cards are available for the 7I43 7I43H These cards include a 4 axis 3A Hbridge a 2 Axis 3A stepper motor driver an analog servo amp interface an RS 422 485 interface and a debug LED card One daughter card can plug directly onto the 7I43 7I43H Many IO configuration files are provided with the 7I43 7I43H including simple remote I O 4 an...

Page 6: ...s For applications that require more than the 450 mA supplied by the host the 7I43 has provisions for external power W6 connects host USB power to the 7I43 s power supplies To use host power W6 must be set to the UP position If external 5Vpower is used W6 must be set to the DOWN position WARNING Connecting an external 5V supply to the 7I43 while W6 is in the UP position and a USB cable connects th...

Page 7: ...cted Note that 3 3V mode is not 5V tolerant The FPGA can be damaged by input voltages greater than 4V in 3 3V mode PRE CONFIGURATION PULL UPS The 7I43 has no pull up resistors on its user I O pins This means that before these pins are configured they will not have a defined state If this is not desired internal pull up resistors on all FPGA pins can be enabled via Jumper W3 When W3 is in the DOWN ...

Page 8: ...7I43 4 CONNECTORS CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS 7I43 U shown P version has different defaults ...

Page 9: ...7I43 5 CONNECTORS 7I43H CONNECTOR LOCATIONS AND DEFAULT JUMPER POSITIONS ...

Page 10: ...tribution disk 7I43 IO connector pinouts are as follows P4 CONNECTOR PINOUT PIN FUNC PIN FUNC PIN FUNC PIN FUNC 1 IO0 2 GND 3 IO1 4 GND 5 IO2 6 GND 7 IO3 8 GND 9 IO4 10 GND 11 IO5 12 GND 13 IO6 14 GND 15 IO7 16 GND 17 IO8 18 GND 19 IO9 20 GND 21 IO10 22 GND 23 IO11 24 GND 25 IO12 26 GND 27 IO13 28 GND 29 IO14 30 GND 31 IO15 32 GND 33 IO16 34 GND 35 IO17 36 GND 37 IO18 38 GND 39 IO19 40 GND 41 IO20...

Page 11: ...GND 7 IO27 8 GND 9 IO28 10 GND 11 IO29 12 GND 13 IO30 14 GND 15 IO31 16 GND 17 IO32 18 GND 19 IO33 20 GND 21 IO34 22 GND 23 IO35 24 GND 25 IO36 26 GND 27 IO37 28 GND 29 IO38 30 GND 31 IO39 32 GND 33 IO40 34 GND 35 IO41 36 GND 37 IO42 38 GND 39 IO43 40 GND 41 IO44 42 GND 43 IO45 44 GND 45 IO46 46 GND 47 IO47 48 GND 49 POWER 50 GND ...

Page 12: ...UT PIN FUNCTION DIRECTION 1 TMS IN 2 TDI IN 3 TDO OUT 4 TCK IN 5 GND 6 3 3V POWER CONNECTOR The 7I43 has an external 5V power connector P1 This connector supplies power to the 7I43 in EPP standalone and USB applications where USB host power is not sufficient to power the 7I43 On 7I43 card with revisions B or less P1 is a four pin 1 male header On 7I43s with revision C or greater or 7I43Hs P1 is a ...

Page 13: ... interface the hosts printer port to the 7I43 P2 PIN DB25 PIN SIGNAL P2 PIN DB25 PIN SIGNAL 1 1 STROBE 2 14 AUTOFD 3 2 PD0 4 15 FAULT 5 3 PD1 6 16 INIT 7 4 PD2 8 17 SELECTIN 9 5 PD3 10 18 GND 11 6 PD4 12 19 GND 13 7 PD5 14 20 GND 15 8 PD6 16 21 GND 17 9 PD7 18 22 GND 19 10 ACK 20 23 GND 21 11 BUSY 22 24 GND 23 12 PERROR 24 25 GND 25 13 SELECT 26 VCC Note All handshake signals are available at the ...

Page 14: ...e control register and the data register The control register is at EPP address 1 and has a single output bit at D0 that controls FPGA PROGRAM and a single input bit at D0 that reads the FPGA s done status The data register at EPP address 0 is used for the byte wide configuration data Reads from the data register will return the FPGA size in D0 1 400K and 0 200K EPP CONFIGURATION PROCEDURE EPPWrit...

Page 15: ...NE status will be returned in the echoed characters LSb If a character with a 0 LSb is sent a character will be echoed indicating the FPGA size This echoed character will have a 0 LSb for 200K 7I43s and a 1 LSb for 400K 7I43s Since it in not desirable to deal with echoed characters for every configuration byte sent to the 7I43 status character echoing is disabled after receiving 4 consecutive char...

Page 16: ...tion The SCM7I43P program is an example program for writing the serial EEPROM via the EPP port DOS only SCM7I43W is a similar example program for writing the serial EEPROM via the USB port windows only The SCM programs rely on EPPIOPR8 for EPP programming or USBIOPR8 for USB configuration file being preloaded into the FPGA before writing the serial EEPROM as the serial EEPROM can only be accessed ...

Page 17: ...TION FILE STARTUP OPTIONS Important Because the 7I43s CPLD stops configuration when DONE is asserted the configuration file startup options must be set so that asserting DONE is the last configuration step Suggested startup options are as follows FPGA STARTUP CLOCK CCLK DONE 6 ENABLE OUTPUTS 5 RELEASE WRITE ENABLE 4 RELEASE DLL NO WAIT SC7I43P and SC7I43W Two utility programs SC7I43P EXE and SC7I4...

Page 18: ...t bidirectional data bus D0 D7 and four handshake lines Note that the handshake lines are fed through the CPLD so depend on the standard CPLD configuration The D bus connects to the FPGA through 100 Ohm resistors These resistors provide 5V tolerance and series line termination for driving the cable P2 PIN EPPNAME SPPNAME FPGA PIN DIRECTION 1 WRITE STROBE 84 TO FPGA 2 DSTROBE AUTOFD 79 TO FPGA 8 AS...

Page 19: ...e VCP Virtual COM Port series drivers The 7I43H uses a FT2232H high speed USB interface chip 480 Mbps Unlike the FT245R used in the 7I43 the FT2232H appears as two serial ports Only the first port is used by the 7I43H The supplied configurations support the same FIFO interface mode as the 7I43 and the same pinout but the 7I43H also has the FPGA connections to support the high speed synchronous mod...

Page 20: ... driven user LEDS These green LEDS are located in the top center of the card They can be used for any purpose and can be helpful as a simple debugging feature A low output signal from the FPGA lights the LED See the 7I43MISC PIN file for FPGA pin locations of the LED signals In addition to the user LEDs there are three other LEDS that display board status information These status LEDS are on the l...

Page 21: ...3V mode is suggested for general use Note that 3 3V mode is not 5V tolerant When the bus switch mode jumper W2 is in the up position 5V mode is selected when down 3 3V bus switch mode is selected IO LEVELS The FPGA used on the 7I43 is a Spartan3 The Spartan3 supports many I O standards The 7I43 does not support use of the I O standards that require input reference voltages also VCCIO is fixed at 3...

Page 22: ...ctive low so that all outputs are in the in active state at power up DRIVING 5V REFERRED LOADS When driving external loads like Solid State Relays SSRs with an active low output and the SSR terminal connected to 5V the 7I43 output should be configured for 5V tolerance and the output should be driven in open drain mode This is because the 7I43 outputs only swing to 3 3V in normal mode leaving 1 7V ...

Page 23: ...TOR 0 0x10 0x20 0 7 P4 1 0x11 0x21 8 15 P4 2 0x12 0x22 16 23 P4 3 0x13 0x23 24 31 P3 4 0x14 0x24 32 39 P3 5 0x15 0x25 40 47 P3 In addition to the GPIO bits the EPPIOPR8 configuration has a simple SPI interface to the configuration EEPROM and a reconfiguration port The SPI port allows the utility program SCM7I43P to write configuration data to the serial EEPROM These registers are mapped as follows...

Page 24: ...onfigurations There are two USBIOPR8 configuration files USBIO8 2 BIT for the 200K and USBIO8 4 BIT for 400K versions of the 7I43 PORT DATA REG DDR IO BITS CONNECTOR 0 0x010 0x020 0 7 P4 1 0x011 0x021 8 15 P4 2 0x012 0x022 16 23 P4 3 0x013 0x023 24 31 P3 4 0x014 0x024 32 39 P3 5 0x015 0x025 40 47 P3 In addition to the GPIO bits the USBIOPR8 configuration has a simple SPI interface to the configura...

Page 25: ...mmands to be executed in response to the single byte command LBP DATA READ WRITE COMMAND 0 1 WR RID AI AS DS1 DS0 Bit 7 6 CommandType Must be 01b to specify data read write command Bit 5 Write 1 to specify write 0 to specify read Bit 4 RPCIncludesData 0 specifies that data is from stream 1 that data is from RPC RPC only ignored for non RPC commands Bit 3 AutoInc 0 leaves address unchanged 1 specif...

Page 26: ...rite Address MSB 0 0 0 0 0 0 0 0 Write data 0 1 0 1 0 1 0 1 0 Write Data 1 1 0 1 1 1 0 1 1 Write Data 2 1 1 0 0 1 1 0 0 Write Data 3 1 1 0 1 1 1 0 1 Write 2 more bytes 0xEE 0xFF at 0x014 and 0x015 COMMAND BITS CT1 CT0 WR RID AI AS DS1 DS0 LBPWrite 0 add 2 data 0 1 1 0 0 0 0 1 Write data 0 1 1 1 0 1 1 1 0 Write data 1 1 1 1 1 1 1 1 1 Read 8 bytes at 0x010 0x011 0x012 0x013 0x014 0x015 0x016 0x017 C...

Page 27: ...ss dont care for USB devices 0xC1 Get LBP status LBP Status bit definitions BIT 7 Reserved BIT 6 Command Timeout Error BIT 5 Invalid write Error attempted write to protected area BIT 4 Buffer overflow error BIT 3 Watchdog timeout error BIT 2 Reserved BIT 1 Reserved BIT 0 CRC error 0xC2 Get CRC enable status 0xC3 Get CRC error count 0xC4 0xC9 Reserved 0xCA Get Enable_RPCMEM access flag 0xCB Get Com...

Page 28: ...7 4 character configuration name only on some configurations 0xD8 Get low address 0xD9 Get high address 0xDA Get LBP version 0xDB Get LBP Unit ID Serial only not used with USB 0xDC Get RPC Pitch 0xDD Get RPC SizeL Low byte of RPCSize 0xDE Get RPC SizeH High byte of RPCSize 0xDF Get LBP cookie returns 0x5A ...

Page 29: ...able_RPCMEM access flag non zero to enable access to RPC memory 0xEB Set Command timeout in mS for USB and character times for serial 0xEC Set Non volatile memory flag 0xED Set External memory flag non zero for external memory mode 0xEE 0xEF Reserved 0xF0 0xF6 Reserved 0xF7 Write LEDs 0xF8 Set low address 0xF9 Set high address 0xFA Add byte to current address 0xFB 0xFC Reserved 0xFD Set unit ID se...

Page 30: ...3 In the USBIOPR8 configuration RPCPitch is 0x10 bytes so each RPC command has native size of 0x10 bytes and start 0x10 byte boundaries in the RPC table area RPCs can cross RPCPitch boundaries if larger than RPCPitch RPCs are needed The stored RPC commands consist of LBP headers and addresses and possibly data if the command header has the RID bit set RPC command lists are terminated by a 0 byte T...

Page 31: ... 0x12 0x13 Command3 Writes a single byte 0xAA to port 0x14 data contained in RPC table COMMAND BITS CT1 CT0 WR RID I AS DS1 DS0 LBPWrite 2 add 2 data 0 1 1 0 0 1 0 1 Write Address LSB 0 0 0 1 0 0 0 0 Write Address MSB 0 0 0 0 0 0 0 0 LBPRead 2 add 2 data 0 1 0 0 0 1 0 1 Read Address LSB 0 0 0 1 0 0 1 0 Read Address MSB 0 0 0 0 0 0 0 0 LBPWrite 2 add 1 data 1 0 1 1 0 1 0 0 Write Address LSB 0 0 0 1...

Page 32: ...isolated I O 7I39 Dual 3 phase H Bridge 7I40 Dual H Bridge 7I42 I O protector 7I44 8 Channel RS 422 to RJ45 breakout 7I46 6 channel SPI breakout 7I47 12 channel encoder oriented RS 422 interface 7I47S 12 channel encoder interface with isolated spindle analog out 7I48 6 channel analog servo interface 7I49 6 channel resolver interface 7I50 SPI I O expander 7I64 24 input 24 output isolated I O 7I65 O...

Page 33: ...ase 5V CURRENTTO P3 P4 2A Typically limited to 150 mA in USB powered case 1 2V CORE POWER CURRENT 1A 1A 300 mA of 5V draw Depends on FPGA configuration MAXIMUM I O I SINK OR I SOURCE 24mA MAXIMUM I O INPUT VOLTAGE 5V 5 5V 5V Tolerant mode I O 0 47 EPP I O MAXIMUM I O INPUT VOLTAGE 5V 4V 3 3V mode I O 0 47 TEMPERATURE C VERSION 0o C 70o C TEMPERATURE I VERSION 40o C 85o C ...