NEC IE-703242-G1-EM1, Preliminary User'S Manual

Page 1: ...Preliminary User s Manual IE 703242 G1 EM1 In Circuit Emulator Option Board for V850ES GB1 Hardware Document No U16345EE1V0UM00 Date Published July 2002 NEC Corporation 2002 Printed in Germany ...

Page 2: ...Note No connection for CMOS device inputs can be cause of malfunction If no connection is provided to the input pins it is possible that an internal input level may be generated due to noise etc hence causing malfunction CMOS devices behave differently than Bipolar or NMOS devices Input levels of CMOS devices must be fixed high or low by using a pull up or pull down circuitry Each unused pin shoul...

Page 3: ...esponsibility of customer NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits software and information While NEC endeavours to enhance the quality reliability and safety of NEC semiconductor products customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely To minimize risks of damage...

Page 4: ...08 588 6000 800 366 9782 Fax 408 588 6130 800 729 9288 NEC Electronics Europe GmbH Duesseldorf Germany Tel 0211 65 03 01 Fax 0211 65 03 327 Sucursal en España Madrid Spain Tel 091 504 27 87 Fax 091 504 28 60 Succursale Française Vélizy Villacoublay France Tel 01 30 67 58 00 Fax 01 30 67 58 99 NEC Electronics Hong Kong Ltd Hong Kong Tel 2886 9318 Fax 2886 9022 9044 NEC Electronics Hong Kong Ltd Seo...

Page 5: ... 2 3 1 Overview 22 2 3 2 Jumper JP2 AVDD selection 22 2 3 3 Jumper JP3 AVSS selection 23 2 4 Main Sockets and Connectors 24 2 4 1 Main Sockets 24 2 4 2 Clock Connectors 24 2 4 3 Other Components 24 2 5 Clock Operation 25 2 5 1 Main Clock 25 2 5 2 Sub Clock 26 Chapter 3 Operating Precautions 29 3 1 Reset source monitor flag 29 3 2 Standby release 29 3 3 Port direction setting for peripheral functio...

Page 6: ...6 Preliminary User s Manual U16345EE1V0UM00 ...

Page 7: ...are configuration 11 Figure 1 2 System Configuration 15 Figure 2 1 IE 703242 G1 EM1 top view 19 Figure 2 2 IE 703242 G1 EM1 bottom view 20 Figure 2 3 LEDs controlled by IE 703242 G1 EM1 21 Figure 2 4 Main Clock Configuration 25 Figure 2 5 Sub Clock Configuration 26 Figure A 1 Mechanical Data 35 ...

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Page 9: ...M1 13 Table 1 3 Functional Specifications of IIE 703242 G1 EM1 14 Table 2 1 LEDs controlled by IE 703242 G1 EM1 21 Table 2 2 Component Overview 22 Table 2 3 Jumper JP2 AVDD selection 22 Table 2 4 Jumper JP3 AVSS selection 23 Table 2 5 Main Sockets 24 Table 2 6 Clock Connectors 24 Table 4 1 Pin list according to their emulation location 32 ...

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Page 11: ...h IE 703242 G1 EM1 1 1 Hardware Configuration Figure 1 1 IE 703242 G1 EM1 hardware configuration Emulation board IE 703242 G1 EM1 Additional Hardware Probe cable SWEX 100SD1 General purpose extension probe cable for target connection Additional Hardware In Circuit Emulator IE V850ES G1 PC Interface Card IE 70000 PCI IF A IE 70000 CD IF A For connection of the IE V850ES G1 to a PC Insert to the res...

Page 12: ...Main board for CPU emulation and trace Notes 1 2 Emulation board IE 703242 G1 EM1 Emulation board for V850ES GB1 Notes 1 2 Probe cable SWEX 100SD1 Probe cable for target connection Note 2 Probe to target connector NQPACK100SD Board socket for target connection soldered on target board Note 2 Probe to target connector YQPACK100SD Probe connection fixed on NQPACK100SD Note 2 Probe to target connecto...

Page 13: ... Please refer to the appendix Mechanical data Parameter Value Operation frequency max 16 MHz Main clock Operation Temperature range 0 to 40 C Storage temperature range 15 to 60 C Environmental humidity range 10 80 RH Supply voltage 4 5 V to 5 5 V 5 Supply current 300 mA Power dissipation 1 W 16 MHz Weight 300 g Dimensions Note 205 mm x 140 mm x 20 mm ...

Page 14: ...for execution pass detection Internal ROM 256 KB External memory 1 MB Coverage memory capacity for memory access detection External memory 1 MB Coverage memory capacity for branching entry number counting Internal ROM 256 KB External memory 1 MB Trace memory capacity 168 bits 32 K frames Time measurement function On chip timer 3 External logic probe 8 bit external trace possible Event setting for ...

Page 15: ... 3 Device file Included with the IE 703242 G1 EM1 4 PC interface board Sold separately 5 PC interface cable Included with the IE V850ES G1 Sold separately 6 Power supply cable Included with the IE V850ES G1 Sold separately 7 In circuit emulator IE V850ES G1 Sold separately 8 In circuit emulator emulation board IE 703242 G1 EM1 This product 9 Extension probe SWEX 100SD1 Sold separately 10 YQPACK100...

Page 16: ...ms 1 Hardware 1 pcs IE 703242 G1 EM1 1 pcs Antistatic bag 6 sets Screws washers 2 Documentation 1 pcs Read me IE 703242 G1 EM1 1 pcs Operating precautions 1 pcs Hardware tool registration card 1 pcs Notification on internet software update provision 1 pcs Read me first 1 pcs User s manual 3 Software Device Files on Floppy Disk ...

Page 17: ...ion to the main board is secured 6 Fix the IE 703242 G1 EM1 to the main board using the screws delivered with the board 7 If the tool is used with a target board for emulation connect the probe adapter SWEX 100SD1 to the appropriate socket SO2 of IE 703242 G1 EM1 8 Close the cover of the IE V850ES G1 9 Reconnect the power to the IE V850ES G1 10 If the tool is used with a target board for emulation...

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Page 19: ...ns of Components This chapter describes the names and functions of the components of IE 703242 G1 EM1 Also jumpers and switches used for configuration of the tool are described here 2 1 Name and Functions of IE 703242 G1 EM1 Components Figure 2 1 IE 703242 G1 EM1 top view ...

Page 20: ...20 Chapter 2 Name and Functions of Components Preliminary User s Manual U16345EE1V0UM00 Figure 2 2 IE 703242 G1 EM1 bottom view ...

Page 21: ... V850ES G1 itself Figure 2 3 LEDs controlled by IE 703242 G1 EM1 Remark For information about external trigger inputs and output refer to IE V850ES G1 User s Manual Table 2 1 LEDs controlled by IE 703242 G1 EM1 Note See 2 4 Main Sockets and Connectors for target power switching LED Colour Function 1 green Target reset 2 green Don t care internal use only 3 green Don t care internal use only 4 yell...

Page 22: ...selection Component Function Described in JP1 Select sub clock signal generated by timer circuit 2 4 2 Clock Connectors JP2 AVDD input voltage selection 2 3 2 Jumper JP2 AVDD selection JP3 AVSS input voltage selection 2 3 3 Jumper JP3 AVSS selection SO1 Socket for alternative main clock oscillator 2 4 2 Clock Connectors SO2 Socket for target connection 2 4 1 Main Sockets CN1 CN2 CN3 Connection to ...

Page 23: ...45EE1V0UM00 2 3 3 Jumper JP3 AVSS selection This function is used to select the input signal for the AVSS pin of the I O chip on the IE 703242 G1 EM1 emulation board Table 2 4 Jumper JP3 AVSS selection Position Function 1 2 default Connect AVSS to target 2 3 Connect AVSS to GND ...

Page 24: ...kets 2 4 2 Clock Connectors These are used to configure clock oscillators of the IE 703226 G1 MC to run at the desired operation frequency Table 2 6 Clock Connectors 2 4 3 Other Components Further connectors and test points are used for internal testing during production and maintenance and are not listed here Socket Function SO2 Socket is used to connect probe adapter SWEX 100SD1 when the In Circ...

Page 25: ...erates at frequencies up to 16 MHz On the emulation board the source for the main clock can either be a crystal or a dedicated C MOS oscillator By default a crystal is used which is assembled to the respective connector CN6 Alternatively a dedicated C MOS oscillator in DIL Package may be used In this case the crystal and capacitors must be removed from CN6 and a crystal oscillator must be mounted ...

Page 26: ...it generates an adjustable frequency in the range of 40 to 100 KHz If the timer circuit is used the sub clock crystal and capacitors must be disconnected from CN9 and jumper JP1 must be shorted By default the timer circuit is configured to operate at a frequency of about 100 KHz To adjust the operating frequency of the sub clock timer circuit R28 R29 and C77 on the emulation board must be changed ...

Page 27: ...nual U16345EE1V0UM00 To change the operation frequency of the oscillator circuit R28 R29 and C77 must be selected using the following formulae Remark Use R28 and R29 in the Range 1 KΩ R 10 MΩ and C77 in the Range 1 nF C 10 µF f 1 44 R28 2 R29 C77 R29 1 2 1 44 f C77 R28 ...

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Page 29: ...mode is released 3 3 Port direction setting for peripheral function When a peripheral function is used the direction setting for the respective port bit of the V850ES GB1 real chip is not set automatically The port bit direction has to be programmed according to the requirement of the peripheral function by setting the port mode register In the FPGA on the emulation board port mode setting is not ...

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Page 31: ...c differs from the real chip 4 4 REGC pin The REGC pin of the target connector is not connected to the corresponding pin of the I O chip On the emulation board a capacitor is connected to the REGC pin of the I O chip internally 4 5 Clock oscillator inputs The pins for main clock connection X1 and X2 as well as the pins for sub clock connection CL1 CL2 XT1 XT2 of the I O chip on the emulation board...

Page 32: ...s 4 P01 P01 INTP1 I Venus 5 P02 P02 INTP2 I Venus 6 P03 P03 INTP3 I Venus 7 P04 P04 INTP4 I Venus 8 P05 P05 INTP5 I Venus 9 VDD50 VDD50 S buffered 10 REGC0 REGC0 S not connected 11 VSS30 VSS30 S Ground 12 X1 X1 I not connected 13 X2 X2 O not connected 14 RESET RESET I buffered 15 XT1 XT1 I not connected 16 XT2 XT2 O not connected 17 NMI NMI I Venus 18 P06 P06 INTP6 I Venus 19 P10 P10 SI00 I Venus ...

Page 33: ...GA via L S 48 PDL5 PDL5 I FPGA via L S 49 PDL6 PDL6 I FPGA via L S 50 PDL7 PDL7 I FPGA via L S 51 PDL8 PDL8 I FPGA via L S 52 PDL9 PDL9 I FPGA via L S 53 PDL10 PDL10 I FPGA via L S 54 PDL11 PDL11 I FPGA via L S 55 PDL12 PDL12 I FPGA via L S 56 PDL13 PDL13 I FPGA via L S 57 VPP VPP S not connected 58 PDL14 PDL14 I FPGA via L S 59 PDL15 PDL15 I FPGA via L S 60 VDD51 VDD51 S buffered 61 VSS51 VSS51 S...

Page 34: ...nus 79 P21 P21 TXD61 I Venus 80 P22 P22 SI01 I Venus 81 P23 P23 SO01 I Venus 82 P24 P24 SCK01 I Venus 83 P25 P25 I Venus 84 P30 P30 TI50 TO50 I Venus 85 P31 P31 TI51 TO51 I Venus 86 P32 P32 TI52 TO52 I Venus 87 P33 P33 TIC00 TOC0 I Venus 88 P34 P34 TIC01 I Venus 89 P711 P711 ANI11 I Venus 90 P710 P710 ANI10 I Venus 91 P79 P79 ANI9 I Venus 92 P78 P78 ANI8 I Venus 93 P77 P77 ANI7 I Venus 94 P76 P76 ...

Page 35: ...35 Preliminary User s Manual U16345EE1V0UM00 Appendix A Mechanical Data Figure A 1 Mechanical Data ...

Page 36: ...36 Preliminary User s Manual U16345EE1V0UM00 MEMO ...

Page 37: ... 24 CN2 24 CN3 24 CN6 24 CN9 24 configuration hardware 11 connection emulation board to IE V850ES G1 17 D differences 31 dimensions 13 E emulation board 12 F frequency operation frequency 13 H humidity environmental humidity 13 I IE 70000 CD IF A 12 IE 70000 MC SV3 12 IE 70000 PCI IF A 12 IE 703242 G1 EM1 12 IE V850ES G1 12 In Circuit Emulator 12 interface network interface card 12 PC interface ca...

Page 38: ...I interface card 12 PCMCIA interface card 12 pin list 32 precautions 29 probe cable 12 R REGC pin 31 reset input pin 31 RSM register 29 S settings clock settings 25 jumper configuration 22 SO1 24 SO2 24 specifications functional 14 standby release 29 status LED 21 supply current 13 voltage 13 SWEX 100SD1 12 T temperature operation 13 storage 13 V view bottom view of emulation board 20 top view of ...

Page 39: ...39 Appendix B Index Preliminary User s Manual U16345EE1V0UM00 W weight 13 Y YQPACK100SD 12 YQSOCKET100SD 12 ...

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