Xerox Sigma 6, Reference Manual

Page 1: ...Xerox SIGMA 6 Computer Reference Manual I...

Page 2: ...Byte String 63 FIXED POINT ARITHMETIC EBS 63 Edit Byte String 64 AI 20 Add Immediate 39 PUSH DOWN AH 50 Add Hallward 39 AW 30 Add Word 40 PSW 09 Push Word 69 AD 10 Add Doub leward 40 PLW 08 Pull Word...

Page 3: ...Xerox SIGMA 6 Computer Reference Manual 90 17 138 June 1971 1970 1971 Xerox Corporation XEROX File No 1X13 XL47 Rev 0 Printed in U S A...

Page 4: ...page RELATm PUBLICATIONS Xerox Sigma Glossary of Computer Terminology Xerox Meta Symbol LN OPS Reference Manual Xerox Symbol lN OPS Reference Manual Xerox Macro Symbol LN OPS Reference Manual Publica...

Page 5: ...44 Logical Instructions 46 Sh ift Instructions 47 Floating Point Shift 48 Conversion Instructions 49 Floating Point Arith metic Instructions 50 Floating Point Numbers 50 Unimplemented Floating Point...

Page 6: ...on of ActuaI Memory Addresses 16 A REFERENCE TABLES 100 6 Typical Interrupt Priority Chain XDS Standard Symbols and Codes 100 7 Operational States of an In errupt Level XDS Standard Character Sets 100...

Page 7: ...6 Computer Sigma...

Page 8: ......

Page 9: ...irect addressing with or without postindexing Displacement index registers automatically self adjusting for all data sizes Immediate addressing of operands for greater storage efficiency and increased...

Page 10: ...ubchonnels One group of eight subchannels I Single byte interface I Single byte interface Single byte interface I Four byte interface I Four byte interface I I Optianal Features Two additional groups...

Page 11: ...tion a 16 bit address is transferred for selection and control purposes Each transfer is under direct program control Is used for the attachment of external units to the direct I O interface External...

Page 12: ...and one group of eight subchannels Selector Input Output Processor SlOP with 4 byte interface REAL TIME FEATURES Real time appl ications are characterized by a need for hard ware that provides quick...

Page 13: ...word arithmetic operations in addition to fullword oper ations Doubleword arithmetic operations for extended precision are also included Direct Data Input Output For handl ing asynchronous I O a 32 b...

Page 14: ...Sharing Multiuse Features User Protection The slave mode of operati on restricts each user to his own set of instructions while reserving to the operating system those instructions that could if used...

Page 15: ...l operations benefit all users because more of the computer s resources are avail able for useful work Memory Protection The memory protection features protect each user from every other user and also...

Page 16: ...ept for memory locations 0 through 15 and by the lOPs The SIGMA6 addressing capabi lity accommodates a maximum memory size of 131 072 words 524 288 bytes Core memory is modular and is available in inc...

Page 17: ...tions are permissible It is assumed that there is a resident execu tive program operating in the master mode that controls and supports the other programs operating in the master or slave mode SLAVE M...

Page 18: ...ddress Flag o III I III I Operation Code Field I 7 ITTIJ General Register Designator 8 11 ITIJ Index Register Designator 12 Reference Address Field 11111111111111111111 I 6 1 t I t I I Iiili 11 il llj...

Page 19: ...ses indirect addresses and addresses used as counts within a s ored program as well as those addresses computed by the program An actual address is a value used by the CPU t access mem ory for storage...

Page 20: ...struction Format and not in a general register or core memory location The operand field of this type of instruction cannot be modified by indexing The following SIGMA 6 instructions are of the immedi...

Page 21: ...ecause an effective address can be either an actual address or a virtual address this definition of an effective location assumes where applicable the trans formation of vi rtual addresses into ac tua...

Page 22: ...rced to O Thus an odd numbered word address referring to the middle of a double word designates the same doubleword as an even numbered word address when used for a doubleword operation MEMORY ADDRESS...

Page 23: ...e address bits in the accessed byte of the memory map replace the 8 high order bits of the virtual address to produce the actua I address of the core memory location to be used by the in struction If...

Page 24: ...d write access to that page is permitted independent of the key value A key value of 00 is a skeletonll key that wi II open any locki thus write access to any memory page is permitted independent of i...

Page 25: ...Float ing point Instructions Any program slave or master can change the state of the current floating point mode controls by executing either the instruc tion LCFI or the instruction LCF any program...

Page 26: ...ity and the last level has the low est The user has the option of ordering a machine with a priority chain starting with the override group and con necting all remaining groups in any sequence This al...

Page 27: ...n this column indicate the bit position in register R that corresponds to the various interrupt levels ttThe numbers in this column indicate the group codes for use with WRITE DIRECT of the various in...

Page 28: ...edictab Ie state registers restored etc Since main frame power supplies maintain voltages for five milliseconds after detecting an imminent power failure the total time of the power on and power off r...

Page 29: ...after the higher priority interrupt is cleared However an interrupt servicing routine cannot be interrupted by a lower priority interrupt as long as it remains in the active state Normally the interr...

Page 30: ...continue 22 Trap System When a modify and test instruction is executed in a count pulse interrupt location all of the above conditions appl in addition to the following If the resultant value in the e...

Page 31: ...aded from memory Set CC3 after new CC is loaded from memory If bit 9 of XPSD is 1 add 2 to the new instruction address value loaded from memory Set CC4 after new CC is loaded from memory If bit 9 of X...

Page 32: ...bi t position 9 of XPSD contains a 1 the instruc tion address loaded from memory is incremented by 2 If bit position 9 of XPSD contains a 0 the instruction address remains at the value loaded from mem...

Page 33: ...e modified only if the instruction is successfully executed The execution of XPSD in trap location X 42 is as follows 1 Store the current PSD The condition code stored is that which existed immediatel...

Page 34: ...esul t with 26 Trap System FS 1 and FN 0 or a postnormalization shift of m more than two hexadecimal places with FS 1 and FN 0 the stored condition code is interpreted as follows CCI CC2 CC3 CC4 Meani...

Page 35: ...e four call instructions CAll CAL2 CAL3 and CAL4 cause the computer to trap to location X 48 for CAll X 49 for CAL2 X 4A for CAL3 or X 4B for CAL4l Execution of XPSD in the trap location is as follows...

Page 36: ...of the instruction word is a 1 the instruction is treated as a nonexistent instruction in which case the computer unconditionally aborts execution of the instruction at the time of operation code deco...

Page 37: ...general register or mem ory word modified by an instruction a shaded area represents a field whose content is indeterminate after execution of the instruction 8 The description of the instruction def...

Page 38: ...ction no index ing is performed If X t a for an instruction in dexing is performed after indirect addressing if indirect addressing is called for with general register X in the current register block...

Page 39: ...ion marks and preceded by the qualifier X for example 7B0 16 is writ ten X 7BO AND Iogi cal product where 0 nO 0 on 1 0 1 n 0 0 and 1 n 1 1 OR logical inclusive OR where 0 u 0 0 ou 1 1 1 u 0 1 and 1 u...

Page 40: ...LOAD HALFWORD Halfword index alignment LOAD HALFWOR D extends the sign of the effective half word 16 bit positions to the left and then loads the 32 bit result into register R Affected R CC3 CC4 EHSE...

Page 41: ...If CC2 is set to 1 and the fixed point arithmetic trap mask AM is a 1 the computer traps to location X 43 after exe cution of LOAD COMPLEMENT WOR D otherwise the com puter executes the next instructi...

Page 42: ...on the two s complement of the effective doubleword rather than the final result in register R Fixed point overflow occurs if the effective doubleword is _ 3 X 8000000000000000 in which case the resul...

Page 43: ...advisable that the register containing the di rect address index displacement or instruction be the last register loaded by the LM instruction If the effective virtual address of the LM instruction i...

Page 44: ...rd location Affected EWl R EWl STD STORE DOUBlEWORD Doubleword index alignment STORE DOU BlEWORD stores the contents of register Rinto the 32 high order bit positions of the effectivedoubleword loca t...

Page 45: ...atus doubleword into the effective byte location as follows Affected EBL PSD O_7 EBL ANALYZE INTERPRET INSTRUCTIONS ANLZ ANALYZE Word index alignment The ANALYZE instruction treats the effective word...

Page 46: ...word into bit positions 20 31 of register R and loads a s into the remai nder of register R and then loads bits 16 31 of the effective word into bit positions 16 31 of register Ru 1 and loads a s int...

Page 47: ...For addition and subtraction the incorrect result is loaded into the designated register sL For a divide in struction the designated register s and CC1 CC3 and CC4 are not affected 2 3 4 Result o no...

Page 48: ...R Ru 1 o 0 o zero negative 40 Fixed Point Arithmetic Instructions o 1 2 o 1 3 4 Result in R Ru1 o positive no fixed point ove flow fixed point overflow no carry from bit position 0 carry from bit posi...

Page 49: ...1 then loads the 32 high order bits of the product into register R and then loads the 32 low order bits of the product into register Rul If R is an odd value the result in register R is the 32 low ord...

Page 50: ...cannot be correctly represented in 32 bits fixed point overflow occurs in which case CC2 is set to 1 and the contents of register R and CC1 CC3 and CC4 are unchanged Affected R CC2 CC3 CC4 Trap Fixed...

Page 51: ...is set according to the result of the test but the effective byte is not affected A memory write protection violation cannot occur in this case however a memory read protection violation can occur Af...

Page 52: ...hmetic trap mask AM is a 1 the computer traps to location X 43 after the result is stored in the effective word location otherwise the computer executes the next instruction in sequence However if MTV...

Page 53: ...word index alignment COMPARE DOUBLEVvORD compares the effective double word with the contents of registers Rand Ru 1 with both doublewords treated as signed fixed point quantities and sets the conditi...

Page 54: ...reater than Ieast signifi cant word R ED 32 _ 63 46 Logical Instructions LOGICAL INSTRUCTIONS All logical operations are performed bit by corresponding bit between two operands one operar d is in regi...

Page 55: ...amount of the shift Theshiftcount C is treated asa7 bit signed binary integer with the high order bit bit position 25 as the sign negative integers are represented in two s complement form A positive...

Page 56: ...for the floating poinj shift instruction is SF SHIFT FLOATING Word index al ignment If indirectaddressing or indexing is called for in the instruction word the effective virtual address is computed as...

Page 57: ...eristic overflow characteristi c overfl ow Floating Shift Single Register The short format floating point number in register R is shifted according to the rules established above for floating point sh...

Page 58: ...e is compared and the process continues through n equal to 31 the remainder in the A register is loaded into register R and the converted quantity in the B register is loaded into register Rul Affecte...

Page 59: ...rd PSD5 7 The_ floating point mode is established by setting the three floating point mode control bits This can be performed by any of the following instructions Instruction Name Load Conditions and...

Page 60: ...2 Floating Point Arithmetic Instructions set equal to true zero the condition code is set to 1000 and the computer executes the next instruction in sequence If more than two hexadecimal place of postn...

Page 61: ...cimal digits long guard digits are not appended to the fractions and R must be an even value for correct re sults If no floating point arithmetic fault occurs the sum is loaded into registers Rand Ru1...

Page 62: ...ting point arithmetic fault occurs the postnormalized product is truncated to a long format floating point number and loaded into registers Rand Ru 1 54 Decimal Instructions Affected R Ru 1 CC R Ru 1...

Page 63: ...1 all have the same functions for the decimal instructions as they do for any other SIGMA 6 byte addressing instruction However bit positions 8 11 of the instruction word do not refer to a general reg...

Page 64: ...or sign has been detected and CC2 to indicate whether or not over flow has occurred Most but notall of the decimal instruc tions provide condition code settings using CC3 and CC4 to indicate whether t...

Page 65: ...ce is equal to or greater then 1031 in which case CCl is reset to 0 CC2 is set to 1 and the instruction is aborted with the contents of the previous decimal accumu lator CC3 and CC4 unchanged Affected...

Page 66: ...Decimal Instructions DC DECIMAL COMPARE Byte index al ignment If there is no illegal digit or illegal sign in the effective decimal operand or in the decimal accumulator DECIMAL COMPARE expands the ef...

Page 67: ...ecimal number in the decimal accu mulator therefore the length of the effective decimal oper and is 2L 1 bytes where L 0 implies a length of 31 bytes for the effective decimal operand This instruction...

Page 68: ...OFOF1F2 F3F4C5 01xx X 00001001 00001002 00001003 0001004F EDO xxxxxxxx xxxxxxxx X FOFOFOFl FOFOC4 CC xxxx 01xx BYTE STRING INSTRUCTIONS Five instructions provide for the manipulation of strings of con...

Page 69: ...tion word the destination address is also the address in register R but without the displacement added Case III R is zero The effective source address is the displacement value in the instruction word...

Page 70: ...tring begins with the byte location 62 Byte String Instructions pointed to by the destination address in register 1 and is C bytes in length In this case the source byte is duplicated throughout the d...

Page 71: ...de decoding and traps to location X 40 with the contents of regi ster R and the destination byte string unchanged Case I even nonzero R field Ru 1 R 1 Contents of register R Contents of register R 1 T...

Page 72: ...displacement in TTBS In this case the instruction aUiomaticaily provides a mask of eight lis This is an exception to the general rule used in the other byte string instructions that register o provide...

Page 73: ...rn bytes are replaced by blank characters X 40 until significance is again present until a field separator is encoun tered or until the destination byte string is entirely processed whichever occurs f...

Page 74: ...positions 13 31 of register 1 bit positions 0 12 of register are unpredictable Mode 2 Load bits 13 31 of register R 1 into bit positions 13 31 of register 1 and then 66 Byte String Instructions 3 4 i...

Page 75: ...the decimal information field are 06 54 32 1 Example 2 after execution The instruction word and the decimal field are unchanged The new contents of registers 6 and 7 are identical to those given for e...

Page 76: ...g stack limit overflow or underflow and with the condition code unchanged from the value it contained before execution of the instruction 68 Push Down Instructions However this trap action can be sele...

Page 77: ...ents of register R into the push down stack defined by the stack pointer doubleword located at the effective doubleword address of PSW If the push operation can be successfully performed the instructi...

Page 78: ...0 0 0 word count ec 215_1 TW 1 0 0 0 space count ec TS 1 0 0 space count ec word count 0 TS 1 0 0 space count ec word count CC 2 15_1 TS 1 and TW 1 0 0 space count 0 TS 1 0 space count 0 word count 0...

Page 79: ...struction may have already overwritten the index direct address or the PLM instruction itself thus destroying any possibility of continuing the program successfully If such programming must be done it...

Page 80: ...dated in struction address by 1 and then traps to the location assigned to the trap condition If neither a trap condition nor a satisfied branch condition occurs during the execution of an instruction...

Page 81: ...ON CONDITIONS SET forms the logical product AND of the R field of the instruction word and the current condition code If the logical product is nonzero the branch condition is satisfied and instructi...

Page 82: ...regis ter R clears bit positions 0 14 of register R to Dis and then replaces the updated instruction address with the effective virtual address Instruction execution proceeds with the instruction poin...

Page 83: ...i if bit S of LPSD is a 0 the current register pointer value remains unchanged 2 If bit position 10 CL of LPS D contains a 1 the highest priority interrupt level currently in the active state is clear...

Page 84: ...ent program status doubleword remain unchanged if any or all of bits 37 38 or 39 of the second effec tive doubleword are Is the corresponding bits in the current program status doubl eword are set to...

Page 85: ...privileged instruction violation 1 CC3 then if 1 9 1 IA 2 IA If memory protection violation 1 CC4 then if 1 9 1 IA 1 IA If call instruction CC u CALLS 11 CC then if 1 9 1 fA CALL8 11 fA If 1 9 0 fA n...

Page 86: ...first registers loaded to be overwritten 78 Control Instructions Each word of the memory map control image is assumed to be in the following format MEMORY MAP LOADING PROCESS Bit positions 15 22 of r...

Page 87: ...n a value equal to the sum of the initial contents plus 4 times the initial word count INTERRUPTION Of MMC The execution of MMC can be interrupted after each word of the control image has been moved i...

Page 88: ...ration of RD can be used to read the control panel SENSE switches In th is case only the condition code is affected 80 Control Instructions READ AND RESET MEMORY FAULT INDICATORS Each core memory modu...

Page 89: ...llowing configuration of WD is used to toggle the CPU program controlled frequency PCF flip flop The output of the PCF flip flop is transmitted to the computer speaker through the AUDIO switch on the...

Page 90: ...e I O address contain a 3 bit device controller code DC in bit positions 25 27 and a 4 bit device code Device in bit positions 28 31 This form of I O address is used for device controllers such as mag...

Page 91: ...s loaded into the IOPcommand address counter associated with the device controller specified by the I O address of the 510 instruction Then if the device is in the automatic mode it requests an order...

Page 92: ...able device busy devi ce manua I device automatic device unusual end device controller ready device controller not operational device controller unavailable device controller busy unassigned incorrect...

Page 93: ...tion if bits 5and 6 are 00 device controller readyll all device controller conditions required for its proper operation are satisfied If bits 5 and 6 are 01 device controller Bit Position Function 5 6...

Page 94: ...on is loaded into register R I St tus I Byte ount I 0 I I I u I 86 Input Output Instructions The status information returned for HIO has the same in terpretation as that returned for the instruction S...

Page 95: ...count information shows the number of bytes remaining to be transmitted in the current operation at the time of the TDV instruction If the value of the R field of TDV is an even value and not 0 the co...

Page 96: ...tions Bit Position Function 8 Incorrect Iength is suppressed as on error by cont coding the SIL flag 0 1 in bit 38 of the command doubleword At the end of the execution of on I O command list this sta...

Page 97: ...data chain 4 Read card store col umns 1 40 data chain 5 Store columns 41 80 end of command chain end of data chain The SIGMA 6 CPU plays a minor role in the execution of an I o operation The CPU execu...

Page 98: ...al information is re quired for a particular operation e g the starting ad dress of a disk seek the memory byte address field of the command doubleword specifies the starting address of the bytes that...

Page 99: ...for Transfer in Channel MEMORY am ADDRESS For all I O commands except Transfer in Channel and Stop bit positions 13 31 of the command doubleword provide for a 19 bit core memory byte address desig nat...

Page 100: ...or 510 HIO and TIO t the program If the SIL flag is 0 an incorrect length is considered an error 92 lOP Command Doublewords Bit Position Function 39 S and the lOP performs as spucified by the HTE and...

Page 101: ...and is lighted when AC power is on The POWER switch is always operative CPU RESET CLEAR The CPU RESET CLEAR switch is used to initialize the cen tral processor When this switch is pressed the followin...

Page 102: ...MODE indicator is lighted when all the fol lowing conditions are satisfied 1 The WATCHDOG TIMER switch is in the NORMAL position 2 The INTERLEAVE SELECl switch is in the NORMAL position 94 Processor C...

Page 103: ...ved to the STEP position while the INSTR ADDR switch is at HOLD the in struction is executed once each time the COMPUTE switch is moved to STEP the INSTRUCTION ADDRESS indicators remain unchanged unle...

Page 104: ...position arld 96 Processor Control Panel is latching in both the upper 1 and lower 0 positions In the center position aDATAswitchrepresentsnochange in the upper or lower position it represents a 1 or...

Page 105: ...r occurs in a memory bank the appropriate indicator is lighted and remains lighted until the indicators are reset When a memory parity error occurs an interrupt pulse is also transmitted to the memory...

Page 106: ...the internal computer clock When the switch is in the CONT continuous po sition the clock operates at normal speed However when the CLOCK MODE is in the inactive center position the c lock enters an...

Page 107: ...considered an error This means that no transmission error halt will result if the first record is either less than or greater than 88 bytes If the record is greater than 88 bytes on Iy the first 88 by...

Page 108: ...mmand Three types of code are shown 1 the 8 bit XDS Standard Computer Code i e the XDS Extended Binary Coded Decima I Interchange Code EBCDIC 2 the 7 bit American National Standard Code for Informatio...

Page 109: ...ol codes in columns 0 and I and their binary representation are exactly the some os those in the ANSCII table except for two interchanges LF NL with NAK and HT with ENQ Characters enclosed in heavy li...

Page 110: ...4 15 21 IF or Nl 11 9 5 0 10 line feed or new line 16 22 SYN 11 9 6 1 6 sync 17 23 ETB 11 9 7 1 7 end of transmission block 18 24 CAN 11 9 8 1 8 cancel 19 25 EM 11 9 8 1 1 9 end of medium lA 26 SUB 11...

Page 111: ...asterisk 5D 93 11 8 5 2 9 right parenthesis 5E 94 11 8 6 3 11 semicolon 5F 95 or 11 8 7 7 14 tilde or logical not On Model 7670 is not available and ANSCII 5 14 60 96 11 2 13 minus dash hyphen 61 97 0...

Page 112: ...54 12 11 8 2 9A through AI are unassigned 98 155 12 11 8 3 9C 156 12 11 8 4 90 157 12 11 8 5 9E 158 12 11 8 6 9F 159 12 11 8 7 AO 160 11 0 8 1 Al 161 11 0 1 A2 162 s 11 0 2 7 3 A3 163 t 11 0 3 7 4 A4...

Page 113: ...A through DF will not be assigned DB 219 12 11 9 8 3 DC 220 12 11 9 8 4 DD 221 12 11 9 8 5 DE 222 12 11 9 8 6 DF 223 12 11 9 8 7 EO 224 0 8 2 EO E1 are unassigned El 225 11 0 9 1 E2 226 S 0 2 5 3 E3 2...

Page 114: ...1A 1B 0 OE OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C E OF 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 10 F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 10 1E MULTIPLICATION TABLE 1 2 3 4 5 6 7 8 9 A B C 0 E F 2...

Page 115: ...10 8 0 23283 06436 53869 62891 x 10 9 0 14551 91522 83668 51807 x 10 10 0 90949 47017 72928 23792 x 10 12 0 56843 41886 08080 14870 x 10 13 0 35527 13678 80050 09294 x 10 14 0 22204 46049 25031 30808...

Page 116: ...3631 488 14680064 15728640 16777 216 33554432 5 6 0005 0006 0021 0022 0037 0038 0053 0054 0069 0070 0085 0086 OlDl 0102 0117 0118 0133 0134 0149 0150 0165 0166 0181 0182 0197 0198 0213 0214 0229 0230...

Page 117: ...614 0615 0616 0617 0618 0619 0620 0621 0622 0623 270 0624 0625 0626 0627 0628 0629 0630 0631 0632 0633 0634 0635 06 36 0637 0638 0639 280 0640 0641 0642 0643 0644 0645 0646 0647 0648 0649 0650 0651 06...

Page 118: ...1382 1383 1384 1385 1386 1387 1388 1389 1390 1391 570 1392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 1406 1407 580 1408 1409 1410 1411 1412 1413 1414 1415 1416 1417 1418 1419 14...

Page 119: ...150 2151 2152 2153 2154 2155 2156 2157 2158 2159 870 2160 2161 2162 2163 2164 2165 2166 2167 2168 2169 2170 2171 2 172 2173 2174 2175 880 2176 2177 2178 2179 2180 2181 2182 2183 2184 2185 2186 2187 21...

Page 120: ...2918 2919 2920 2921 2922 2923 2924 2925 2926 2927 B70 2928 2929 2930 2931 2932 2933 2934 2935 2936 2937 2938 2939 2940 2941 2942 2943 B80 2944 2945 2946 2947 2948 2949 2950 2951 2952 2953 2954 2955 29...

Page 121: ...674 3675 3683 3684 3685 3686 3687 3688 3689 3690 3691 3699 3700 3701 3702 3703 3704 3705 3706 3707 3715 3716 3717 3718 3719 3720 3721 3722 3723 3731 3732 3733 3734 3735 3736 3737 3738 3739 3747 3748 3...

Page 122: ...00 408046 87500 3C 00 00 00 23437 50000 7C 00 00 00 48437 50000 30 000000 23828 12500 70 00 00 00 408828 12500 3E 000000 24218 75000 7E 00 00 00 409218 75000 3F 00 00 00 24609 37500 7F 00 00 00 409609...

Page 123: ...05E 0000 00143 43261 009E 0000 00241 08886 00 DE 0000 00338 74511 00 1F 0000 00047 30224 005F 0000 00144 95849 009F 00 00 00242 61474 00 DF 0000 00340 27099 00 20 0000 0004d 82812 0060 0000 00146 4843...

Page 124: ...00000 70929 00000 71525 00000 72121 00000 7271 7 00000 73313 00000 73909 00000 74505 00000 75101 00000 75697 Hexadecimal 00 00 80 00 00 00 81 00 00 00 82 00 0000 83 00 00 00 84 00 00 00 85 00 00 00 86...

Page 125: ...69 00 00 00 5E 00000 00218 0000009E 00000 00367 000000 DE 00000 0051 6 000000 1F 0000000072 0000005F 0000000221 0000 00 9F 00000 00370 000000 DF 00000 0051 9 00000020 00000 00074 00000060 00000 00223...

Page 126: ...210 854 715 202 003 717 422 485 351 562 5 140 737 488 355 328 47 0 000 000 000 000 007 105 427 357 601 001 858 711 242 675 781 25 281 474 976 710 656 48 0 000 000 000 000 003 552 713 678 800 500 929 3...

Page 127: ...tive doubleword in a double word operation Effective byte Effective byte location Effective doubleword Effective doubl eword location Effective halfword Effective ha Ifword location Effective word Eff...

Page 128: ...BASIC SIGMA 6 INSTRUCTION EXECUTION CYCLE 120 Appendix B 1 15 33 X 13 31 15 331 EB C24 31 0 C0 23 0 0 EW C 0 0...

Page 129: ...BASIC SIGMA 6 INSTRUCTION EXECUTION CYCLE cont o yes Appendix B 121...

Page 130: ...122 Appendix B FLOATlNG POINT INSTRUCTION EXECUTION FLOAnNG POINT MULnpUCAnON AND DIVISION yes no no...

Page 131: ...and increment its character istic by 1 far each hex place shifted until the characteristics of the num ben are equal FLOATING POINT ADDITION AND SUBTRACTION yes yes pastnarmalization __ __ required m...

Page 132: ...y I and dec rement shift count by I 124 Appendix B Form the 2 s comple ment of the final floating point number 0 Ce3 I CC4 FLOATING POINT SHIFT yes yes no yes RIGHT SHIFT Shift fraction risht 1 hex pl...

Page 133: ...EDIT BYTE STRING INSTRUCTION EXECUTION Fill R O_7 SA R I3 31 0 1 12_31 C Ru 1 0 7 DA Ru 1 13 31 a byte buffer IJ byte buffer II digit buffer d X 2O X 21 h X 22 i X 23 Appendix B 125...

Page 134: ...rd 45 CVA 29 Convert by Addition Word 49 CVS 28 Convert by Subtraction Word 50 CW 31 Compare Word Word 45 DA 79 Decimal Add Byte 57 DC 70 Decimal Compare Byte 58 DD 7A Decimal Divide Byte 58 DH 56 Div...

Page 135: ...Word 44 MW 37 Multiply Word Word 42 OR 49 OR Word Word 46 PACK 76 Pack Decimal Dig its Byte 59 PlM OA Pull Multiple Word 70 PlW 08 Pull Word Word 69 PSM OB Push Multiple Word 70 PSW 09 Push Word Word...

Page 136: ...r 2 the register pointer in the current program status doubleword selects one of the register blocks in the range from XI 41 through Xl l P 4 through 31 decimal The times given in Table D 2 where the...

Page 137: ...3 2 3 2 I 3 2 r f r t f_ ___ 2 _9_ 3 3 1 4 2 0 2 3 2 6 1 5 2 2 2 4 2 9 CBS 2 j N N N N r f I f_ I i if_ ii _t _ _ i__ __I CD 2 9 3 6 3 9 4 2 2 9 3 7 3 9 4 3 2 4 3 0 3 3 3 6 2 5 3 2 3 4 3 8 t r f f f _...

Page 138: ...6 _0_ _ 6 4 min __ __ _ _ 4 2 4 6 3 3 _ 4 0 _ 4 2 _r 4 7_ r _3_ _3_ _ _ 3 9 4 2 4 6 3 3 _ 4 0 _t 4 2_ _4_ _7_ 1 F5S mox I 11 8 2 8 9 9 I 9 5 8 2 9 0 9 I 9 6 8 2 8 9 9 I 9 5 8 2 9 0 9 I 9 6 f__ _ _ _ 1...

Page 139: ...9 10 5 10 5 r RO j nt e rn a t 2 I2 5_ 3 1 1 3 I 2 5 3 1 3 1 2 5 2 5 3 1 3 1 2 5 2 5 3 1 I 3 I RO external 2 8 I 1 8 3 4 I 3 4 2 8 2 83 4 1 3 4 2 8 2 8 1 3 4 1 3 4 2 8 i 2 8 3_4 I 3 4 17 0 41 t 0 I __...

Page 140: ...4N 1 3N 1 3N 1 3N 1 3N 1 3N 1 3N 1 3N 1 3N tl 3N 1 3N 1 3N 1 12 2 1 3N _t_ r __ _1 _4 __t _ WAIT 21 1 9 1 9 2 6 2 6 1 9 1 9 2 7 2 7 1 8 1 8 2 4 2 4 1 9 1 9 2 5 i 2 5 WD internol 2 5 2 5 3 1 3 I 2 5 2...

Page 141: ...A o 1 4 L4 0 4 0 4 0 7 0 7 I 1 _ __I DST 0 30 0 30 1 5 1 5 0 4 0 4 0 7 0 7 ow 1 5 0 8 1 4 1 4 0 4 0 3 0 8 0 6 EBS 25 OAN 0 3 EOR 1 4 0 7 1 4 1 5 0 4 0 3 0 8 0 6 r_ _ _ _ f _ _ _1 __i EXU 26 1 5 0 7 1...

Page 142: ...Notes 22 23 24 25 26 27 28 29 0 5 0 5 1 4 1 4 0 3 0 3 No memory overlap Maximum memory overlap One byte string is in registers Decimal number is in registers Add factor for object instruction 0 6 0 6...

Page 143: ...etic instructions 39 25 floating point arithmetic instructions 53 26 122 123 luad store instructions 31 push down instructions 68 25 Shift instructions 47 49 control instructions 75 82 Con fro I order...

Page 144: ...xistent 22 23 76 privileged 75 88 push down 67 72 25 Shift 47 49 124 translate 63 6 unimplemented 24 23 52 interleave overlap 97 Interpret instruction 38 6 interrupt active 21 armed 20 81 136 Index L...

Page 145: ...ons 47 49 124 significance control floating point 52 17 26 35 37 single instruction interrupt 22 slave mode 9 17 stack pointer doubl eword 68 70 standard features 4 states of an interrupt level 20 Sto...

Page 146: ...erence o Maintaining o Operating Illustrated What is your overall rating of this publication What is your occupation o Very Good o Fair o Very Poor o Good o Poor Your other comments may be entered her...

Page 147: ...T CLASS PERMIT NO 59153 LOS ANGELES CA 90045 POSTAGE WILL BE PAID BY ADDRESSEE HONEYWELL INFORMATION SYSTEMS 5250 W CENTURY BOULEVARD LOS ANGELES CA 90045 ATTN PROGRAMMING PUBLICATIONS Honeywell NO PO...

Page 148: ...mediate 39 61 MBS Move Byte 5tri 9 61 21 CI Compore Immediate 63 EBS Edit Byte String 64 22 LI Load Immediote 32 64 BDR Branch on Decrementing Register 74 23 MI Multiply Immediate 41 65 BIR Branch on...

Page 149: ...InformMIon In the U S A 200 SmIII i SIrMt MS Wllltham 02154 In c neda 2025 SheppMI Avenue E WIIIowdIIe 0rUri0 M2J 1W5 In Mexico Avenidl Nuevo Leon 250 Mexico 11 D F 24778 3C1079 Printed In U S A XL47...