Acces I/O products M.2-AI12-16 Hardware Manual Download

Page: 10 / 14

ACCES I/O Products, Inc.

MADE IN THE USA

mPCIe- and M.2-AIO16-16F Family Manual

Rev B7a

WDG:

If WDG is SET then the Watchdog Timer has Barked (timed out). Refer to Watchdog Control (+4C) for details on using the Watchdog Timer feature.

EXT

If EXT

is SET then an IRQ has been fired from the DIO

Secondary Function “External IRQ

”. Refer to DIO Control (+48) for details on DIO Secondary Functions.

LDAC:

If LDAC is SET then an IRQ has been fired from the DIO 1 Secondary Function “LDAC”. Refer to DIO Control (+48) for details o

n DIO Secondary Functions.

FOF:

If FOF is SET then an IRQ has been fired because the ADC FIFO has Overrun: More data was acquired than fit in the ADC FIFO.

FAF:

If FAF is SET then an IRQ has been fired because the ADC FIFO Count (+28) has reached the configured FIFO Almost Full IRQ Threshold (+20).

DTO:

If DTO is SET then a DMA Timeout IRQ has been fired.

DDONE:

If DDONE is SET then a DMA Done IRQ has been fired.

ADCSTART:

If ADCSTART is SET then an IRQ has been fired from the DIO 0 Secondary Function “ADCSTART”. Refer to DIO Control (+48) for d

etails on DIO Secondary Functions.

ADCTRIG:

If ADCTRIG is SET then an IRQ has been f

ired from the DIO 0 Secondary Function “ADCTRIG”. Refer to DIO Control (+48) for details on DIO Secondary Functions.

enDACFHE: If enDACFHE is SET then an IRQ will fire when the DAC Waveform FIFO drops below half (FDS models only). The IRQ status bit is defined in +4 read.

Bits D9 through D0 indicate if the corresponding IRQ has been enabled.

Write IRQ Status bits SET to clear the latched IRQ Status bit(s). Typically, code will read +40 and write the value to +40 to clear all detected IRQs and leave the IRQ enables unchanged.

Write IRQ Enable bits SET to enable corresponding IRQ sources.

DIO Data, 44 of 32-bit Memory BAR[1]Read/Write 32-bits only

bit D31 through D2

Name UNUSED

DIO1

DIO0

Read DIO Data to read the digital input pins or to readback the last commanded digital output state.

Write to DIO Data to configure the digital pin(s)’ high/low state for those bits in I/O Groups configured as Outputs. SET bi

ts will output high voltage, CLEAR bits will output GND.

Refer to DIO Control (+48) for how to configure the input vs output direction of each I/O Group.

DIO Control, 48 of 32-bit Memory BAR[1]Read/Write 32-bits only

bit

D31…D27

D26

D25

D24

D23

D22

D21

D20

D19

D18

D17

D16

D15 … D2

Name UNUSED enWDG edgeEXT1 enEXT1 edgeEXT0 enEXT0 edgeLDAC enLDAC edgeSTART

enSTART edgeTRIG

enTRIG

UNUSED

I/O Group 1

I/O Group 0

Write DIO Control to enable Digital Secondary Functions, and to control the input vs output direction of each Digital I/O Group.

enWDG:

SET enWDT to enable the “WDT Output Status” Digital Output Secondary Function on DIO 1. DIO 1 (I/O Group

1) becomes an output and indicates the state of

the Watchdog Feature.

enEXT

SET enEXT0 or enEXT1 to enable the corresponding

“External IRQ” Digital Input Secondary Function on DIO

0/1 so the selected edge on the input will

(optionally) generate IRQs.

enLDAC:

SET enLDAC to enable the “External LDAC” Digital Input Secondary Function on DIO

1 so the selected edge will cause the DACs to update and optionally

generate an IRQ.

enSTART:

SET enSTART to enable the “ADC Start Conversion” Digital Input Secondary Function

on DIO 0 so the selected edge will cause an ADC Start Event and optionally

generate an IRQ.

enTRIG:

SET enTRIG to enable the “ADC Trigger”

Digital Input Secondary Function on DIO 0 so the selected edge will trigger timed ADC conversions and optionally

generate an IRQ. Consult the “Software Tips” section for details on using ADC Trigger.

Each Digital Input Secondary function has a configurable active edge, rising or falling. SET the corresponding edge

XXX

bit to select rising edge, CLEAR the bit for falling edge.

Summary of Contents for M.2-AI12-16

Page 1: ...t 800 326 1649 http accesio com mPCIe AIO16 16F http accesio com M 2 AIO16 16F San Diego CA 92121 1506 USA sales accesio com MADE IN THE USA 16 ANALOG INPUT 4 ANALOG OUTPUT 2 DIGITAL I O FOR M 2 AND PCI EXPRESS MINI CARD HARDWARE MANUAL MODELS M 2 AND MPCIE AIO16 16F FAMILY ...

Page 2: ... to 10V 2 5V 5V 10V Outputs Drive 10mA Guaranteed FDS models support Waveform playback on 1 2 3 or 4 DACs simultaneously at up to 1MHz aggregate Onboard Watchdog with status output RoHS compliant standard CHAPTER 3 HARDWARE This manual applies to the following models VENDEV M 2 mPCIe AIO16 16FDS A D 16 bit 2Msps 4 D A w timed DAC Waveform playback 494F C0EB M 2 mPCIe AIO16 16F A D 16 bit 2Msps 4 D...

Page 3: ...milar devices where physical dimension is often the paramount design constraint In Data Acquisition and Control applications low weight and vibration tolerance tend to be of more concern CHAPTER 6 I O INTERFACE Most customers will use the optional cable assembly CAB mPCIe AIOs D Sub Miniature 37 pin Male connector For Singled Ended analog inputs connect GND to ADC COMMON A Note About Unused Analog...

Page 4: ...er at CH0 1 0 Advanced Sequence Acquires Channel 0 using the gain selected via 18 bits 2 0 Conversion starts will automatically cycle through the channels from CH0 through INx2 0 and each channel is acquired at the per channel gain set in 18 The sequence repeats starting at CH0 after INx2 0 is acquired 1 1 Basic Sequence Acquires channel 0 using the gain set in Gain2 0 Conversion starts will autom...

Page 5: ...n control bit and status 4 RW DAC Control Status DAC LTC2664 Command Register bits and DAC status bits 8 W DAC Waveform Divisor DAC Waveform Points second divisor Base Clock DAC Waveform Rate this register C R Base Clock Frequency of the ADC Sequencer Base Clock Hz used to calculate the ADC Rate Divisor for desired conversion rates 10 W R ADC Rate Divisor ADC Start Rate Base Clock ADC Rate Divisor...

Page 6: ... will reset the Analog Input circuits to their power on reset state see each ADC Register for more details RST BOARD Writing a 1 will reset the entire device to its power on reset state All RST bits are command bits a 1 causes the reset to occur and the reset clears the 1 DAC Control Offset 4 of 32 bit Memory BAR 1 Read Write 32 bits only bit D31 D30 D29 D28 D27 D24 D23 through D20 D19 through D16...

Page 7: ...te 32 bits only bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSV AIN 7 GAIN2 0 RSV AIN 6 GAIN2 0 RSV AIN 5 GAIN2 0 RSV AIN 4 GAIN2 0 RSV AIN 3 GAIN2 0 RSV AIN 2 GAIN2 0 RSV AIN 1 GAIN2 0 RSV AIN 0 GAIN2 0 Each nybble configures the gain of the corresponding Analog Input channel ONLY when the ADC is running in Advance...

Page 8: ...NUSED 0 VALID RSV DIO1 DIO0 RSV RSV TEMP MUX SEQ Channel2 0 Diff Gain2 0 ADC Counts Two s complement ADC FIFO Data Read the RAW format ADC Conversion results in twos complement 16 bit form and the associated status word INVALID If INVALID is SET then all other bits are undefined and the entry should be discarded This can occur if you read from the ADC FIFO while the ADC FIFO Count 28 is zero RUNNI...

Page 9: ... differential mode is set and each conversion will be the measurement between the IN and IN pins Gain2 0 If BASIC or non sequenced mode is configured via the SEQ1 0 bits then Gain2 0 selects the gain to be used for the conversion s commanded If advanced sequence mode is configured then these bits are ignored bits 2 0 at 18 take precedence in advanced sequencer mode MUX All users should set this bi...

Page 10: ...ite 32 bits only bit D31 through D2 D1 D0 Name UNUSED DIO1 DIO0 Read DIO Data to read the digital input pins or to readback the last commanded digital output state Write to DIO Data to configure the digital pin s high low state for those bits in I O Groups configured as Outputs SET bits will output high voltage CLEAR bits will output GND Refer to DIO Control 48 for how to configure the input vs ou...

Page 11: ... bits only DAC Waveform FIFO Write DAC commands to load the DAC Waveform FIFO Generally 0x000nCCCC where n is the DAC and CCCC is the counts Read returns the number of control values currently in the FIFO FDS models only DAC Waveform DACs Point Offset 54 of 64 bit Memory BAR 2 3 Read Write 32 bits only DAC Waveform DACs Point Write 1 2 3 or 4 to specify how many DACs are being used for Waveform Pl...

Page 12: ... can see an additional 7µs per transaction a modern computer might see 3µs or less Any transaction from the kernel itself however avoids this additional overhead Real time operating systems will enable the highest transaction rates possible all the way up to the hardware limits The latest information can always be found on the product page on the website Here are some useful links Links to useful ...

Page 13: ...ting Female D Sub Miniature 37 pin Model Options T Extended Temperature Operation 40 to 85 C I ID 4 20mA inputs Singled ended Differential PD Pull downs on digital bits Sxx Special configurations 10 50mA inputs input voltage dividers conformal coating etc CHAPTER 9 CERTIFICATIONS CE FCC These devices are designed to meet all applicable EM interference and emission standards However as they are int...

Page 14: ... package All units components should be properly packed for handling and returned with freight prepaid to the ACCES designated Service Center and will be returned to the customer s user s site freight prepaid and invoiced COVERAGE FIRST THREE YEARS Returned unit part will be repaired and or replaced at ACCES option with no charge for labor or parts not excluded by warranty Warranty commences with ...

Search results

Summary of Contents for M.2-AI12-16

Reviews:

Related manuals for M.2-AI12-16

Brands by name

Popular brands

Acces I/O products M.2-AI12-16, Hardware Manual

Search results

Summary of Contents for M.2-AI12-16

Reviews:

Related manuals for M.2-AI12-16

Brands by name

Popular brands