Advantech MIC-3620, User Manual

16 

4.1    Register Structure                                      

This appendix gives short descriptions of each of the module's registers. For more 

information please refer to the data book for the OX16C954 UART chip. 

All registers are one byte. Bit 0 is the least significant bit, and bit 7 is the most 

significant bit. The address of each register is specified as an offset from the port 

base address (BASE). 

DLAB is the "Divisor Latch Access Bit”, bit 7 of BASE+3.   

BASE+0 Receiver buffer register when DLAB=0 and the operation is a read. 

BASE+0 Transmitter holding register when DLAB=0 and the operation is a write. 

BASE+0 Divisor latch bits 0 - 7 when DLAB=1.   

BASE+1 Divisor latch bits 8 - 15 when DLAB=1 

The two bytes BASE+0 and BASE+1 together form a 16-bit number, the divisor, 

which determines the baud rate together with the values of TCR and CPR and Bit7 

of MCR (Modem Control Register)  (refer to 16C954 datasheet). The formula to 

set BaudRate as follows:   

In formula, 

SC

 is sample clock value defined by TCR, when TCR=0x00,

 SC 

=16. 

Prescaler

 is defined by MCR[7] and CPR. 

Prescaler =

 1 when MCR[7] = ‘0’; 

Prescaler =

 M+(N / 8), when MCR[7] =‘1’,   

where:  M = CPR[7:3] (Integer part – 1 to 31) 

N = CPR[2:0] (Fractional part – 0.000 to 0.875 ) 

While Bit7 of MCR is Logic”1”, TCR=0x00 and CPR=0x40, set the divisor as 

follows: 

Baudrate 

Divisor 

Baudrate 

Divisor 

50 

2304 

3600 

32 

75 

1536 

4800 

24 

150 

768 

7200 

16 

300 

384 

9600 

12 

600 

192 

19200 

6 

1200 

96 

38400 

3 

1800 

64 

57600 

2 

2400 

48 

115200 

1 

Table 4-1