June 2012
Altera Corporation
Stratix V Hard IP for PCI Express
12. Flow Control
Throughput analysis requires that you understand the Flow Control Loop, shown in
“Flow Control Update Loop” on page 12–2
. This chapter discusses the Flow Control
Loop and strategies to improve throughput. It covers the following topics:
■
■
Throughput of Non-Posted Reads
Throughput of Posted Writes
The throughput of posted writes is limited primarily by the Flow Control Update loop
shown in
. If the write requester sources the data as quickly as possible,
and the completer consumes the data as quickly as possible, then the Flow Control
Update loop may be the biggest determining factor in write throughput, after the
actual bandwidth of the link.
shows the main components of the Flow Control Update loop with two
communicating PCI Express ports:
■
Write Requester
■
Write Completer
PCI Express Base Specification 3.0
describe, each transmitter, the write requester
in this case, maintains a
credit
limit
register and a
credits
consumed
register. The
credit
limit
register is the sum of all credits issued by the receiver, the write
completer in this case. The
credit
limit
register is initialized during the flow control
initialization phase of link initialization and then updated during operation by Flow
Control (FC) Update DLLPs. The
credits
consumed
register is the sum of all credits
consumed by packets transmitted. Separate
credit
limit
and
credits
consumed
registers exist for each of the six types of Flow Control:
■
Posted Headers
■
Posted Data
■
Non-Posted Headers
■
Non-Posted Data
■
Completion Headers
■
Completion Data
June 2012
<edit Part Number variable in chapter>