Coprocessor Interface
7-6
Copyright © ARM Limited 2000. All rights reserved.
7.2.1
Coprocessor handshake states
The handshake signals encode one of four states:
ABSENT
If there is no coprocessor attached that can execute the coprocessor
instruction, the handshake signals indicate the ABSENT state. In this
case, the ARM9E-S takes the undefined instruction trap.
WAIT
If there is a coprocessor attached that can handle the instruction, but not
immediately, the coprocessor handshake signals are driven to indicate
that the ARM9E-S processor core must stall until the coprocessor can
catch up. This is known as the busy-wait condition. In this case, the
ARM9E-S processor core loops in an IDLE state waiting for
CHSEX[1:0] to be driven to another state, or for an interrupt to occur.
If CHSEX[1:0] changes to ABSENT, the undefined instruction trap is
taken.
If CHSEX[1:0] changes to GO or LAST, the instruction proceeds as
described below.
If an interrupt occurs, the ARM9E-S processor is forced out of the
busy-wait state. This is indicated to the coprocessor by the CPPASS
signal going LOW. The instruction is restarted later and so the
coprocessor must not commit to the instruction (it must not change any
coprocessor state) until it has seen CPPASS HIGH, at the same time as
the handshake signals indicate the GO or LAST condition.
GO
The GO state indicates that the coprocessor can execute the instruction
immediately, and that it requires another cycle of execution. Both the
ARM9E-S processor core and the coprocessor must also consider the
state of the CPPASS signal before actually committing to the instruction.
For an
LDC
or
STC
instruction, the coprocessor instruction drives the
handshake signals with GO when two or more words still have to be
transferred. When only one more word remains to be transferred, the
coprocessor drives the handshake signals with LAST.
During the Execute stage, the ARM9E-S processor core outputs the
address for the
LDC
/
STC
. Also in this cycle, DnMREQ is driven LOW,
indicating to the ARM946E-S memory system that a memory access is
required at the data end of the device. The timing for the data on
CPDOUT and CPDIN is shown in Figure 7-2 on page 7-4.
LAST
You can use an
LDC
or
STC
for more than one item of data. If this is the
case, possibly after busy-waiting, the coprocessor drives the coprocessor
handshake signals with a number of GO states, and in the penultimate
cycle LAST (LAST indicating that the next transfer is the final one). If
there is only one transfer, the sequence is [WAIT,[WAIT,...]],LAST.
Summary of Contents for ARM946E-S
Page 1: ...ARM DDI 0155A ARM946E S Technical Reference Manual ...
Page 6: ...vi Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A 04 Limited Confidential ...
Page 54: ...Programmer s Model 2 34 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Page 70: ...Caches 3 16 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Page 78: ...Protection Unit 4 8 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Page 112: ...Coprocessor Interface 7 14 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...