Programmers Model
ARM DDI 0432C
Copyright © 2009 ARM Limited. All rights reserved.
3-9
ID112415
Non-Confidential
3.4
Memory model
The processor contains a bus matrix that arbitrates the processor core and optional
Debug Access Port
(DAP) memory accesses to both the external memory system and
to the internal NVIC and debug components.
Priority is always given to the processor to ensure that any debug accesses are as
non-intrusive as possible. For a zero-waitstate system, all debug accesses to system
memory, NVIC, and debug resources are completely non-intrusive.
The system memory map is ARMv6-M architecture compliant, and is common both to
the debugger and core accesses. Transactions are routed as follows:
•
All accesses below
0xE0000000
or above
0xF0000000
appear as AHB-Lite
transactions on the AHB-Lite master port of the processor.
•
Accesses in the range
0xE0000000
to
0xEFFFFFFF
are handled within the processor
and do not appear on the AHB-Lite master port of the processor.
The processor supports only word size accesses in the range
0xE0000000
-
0xEFFFFFFF
.
Table 3-2 shows the code, data, and device suitability for each region of the memory
map.
Table 3-2 Memory map usage
Address range
Code
Data
Device
0xF0000000
-
0xFFFFFFFF
No No Yes
0xE0000000
–
0xEFFFFFFF
No
No
No
a
a. Space reserved for Cortex-M0 NVIC and debug
components.
0xA0000000
–
0xDFFFFFFF
No
No
Yes
0x60000000
–
0x9FFFFFFF
Yes
Yes
No
0x40000000
–
0x5FFFFFFF
No
No
Yes
0x20000000
-
0x3FFFFFFF
Yes
b
b. Cortex-M1 devices implementing data
Tightly-Coupled Memories
(TCMs) in this region
do not support code execution from the data TCM.
Yes
No
0x00000000
-
0x1FFFFFFF
Yes
Yes
No
