3-3
However, the software watchdog is programmed for Level 7, priority 2 and uninitialized vector. The
UART1 is programmed for Level 3, priority 2 and autovector. The UART2 is programmed for Level 3,
priority 1 and autovector. The M-Bus is at Level 3, priority 0 and autovector. The Timers are at Level 5
with Timer 1 with priority 3 and Timer 2 with priority 2 and both for autovector.
The SBC5307 uses -IRQ7 to support the ABORT function using the ABORT switch S1 (red switch). This
switch is used to force a non-maskable interrupt (level 7, priority 3) if the user's program execution should
be aborted without issuing a RESET (refer to Chapter 2 for more information on ABORT). Since the
ABORT switch is not capable of generating a vector in response to level seven interrupt acknowledge from
the processor, the debugger programs this request for autovector mode.
The -IRQ1 line of the MCF5307 is not used on this board. However, the -IRQ1 is programmed for Level 1
with priority 1 and autovector. The user may use this line for external interrupt request. Refer to
MCF5307 User’s Manual for more information about the interrupt controller.
3.1.7.
Internal SRAM
The MCF5307 has 4K bytes of internal memory. This memory is mapped to 0x00800000 and is not used
by the dBUG. It is available to the user.
3.1.8.
The MCF5307 Registers and Memory Map
The memory and I/O resources of the SBC5307 are divided into three groups, MCF5307 Internal, External
resources, and the ethernet controller. All the I/O registers are memory mapped.
The MCF5307 has built in logic and up to eight chip-select pins (/CS0 to /CS7) which are used to enable
external memory and I/O devices. In addition there are two -RAS lines for DRAM’s. There are registers to
specify the address range, type of access, and the method of -TA generation for each chip-select and -RAS
pins. These registers are programmed by dBUG to map the external memory and I/O devices.
The SBC5307 uses chip-select zero (/CS0) to enable the Flash ROM’s (refer to Section 3.3.) The
SBC5307 uses /RAS1, /RAS2, /CAS0, /CAS1, /CAS2, and /CAS3 to enable the SDRAM DIMM module
(refer to Section 3.2), /CS2 for SRAM (not populated), and /CS3 for Ethernet Bus I/O space.
The chip select mechanism of the MCF5307 allows the memory mapping to be defined based on the
memory space desired (User/Supervisor, Program/Data spaces).
All the MCF5307 internal registers, configuration registers, parallel I/O port registers, DUART registers
and system control registers are mapped by MBAR register at any 1K-byte boundary. It is mapped to
0x10000000 by dBUG. For complete map of these registers refer to the MCF5307 User's Manual.
The SBC5307 board can have up to 8M bytes of SDRAM installed. The first 8M bytes are reserved for
this memory. Refer to Section 3.2 for a discussion of RAM. The dBUG is programmed in two 29LV004B
Flash ROM’s which only occupies 1M bytes of the address space. The first 128K bytes are used by ROM
Monitor and the second half is left for user. Refer to section 3.3.
The Ethernet Bus interface maps all the I/O space of the Ethernet bus to the MCF5307 memory at address
$FE600000. Refer to section 3.6.
