Peripheral I/O
2-8
CA386-N1 REFERENCE MANUAL
2.5 Peripheral I/O
Most of the common peripherals of a standard PC compatible computer are integrated into the 386EX chip. The
user should consult the Intel 386EX Embedded Microprocessor Hardware Reference manual for more informa-
tion about peripheral mapping and configuration.
The I/O space of the CA386-N1 is compatible with a standard PC and all standard I/O addresses supported by the
386EX are in their normal places. Extended I/O address mode is enabled at boot. Table 2.1 gives the I/O address
map for the CA386-N1 peripherals which are not part of the standard PC I/O space.
The CA386-N1 supports 16 digital I/O lines. Eight of these lines are input only. They exist on JP9 and can be
read as a single byte at I/O location 0x38e. If adjacent pins on JP9 are left open then a ‘1’ is read. Otherwise if a
shorting block is installed a ‘0’ is read.
The other 8 I/O lines are general purpose and connected directly to PORT1 of the 386EX CPU. They can be
accessed by the user as I/O lines DIO0 - DIO7 on J6. This port has three configuration registers and one status
register associated with it. The status register can be set as follows:
•
P1CFG (0xf820) - This should always be set to 0x00 to use PORT1 as a digital I/O port.
•
P1DIR (0xf864) - This selects the direction and function of a bit. Setting a bit in this register to '1' sets
the corresponding I/O to either an input or an open-drain output. Likewise setting a bit to ‘0’ sets the
corresponding bit to be a complementary output.
•
P1LTC (0xf862) - This bit selects the desired output for an I/O pin in output mode.
Table 2.2 shows the possible pin configurations.
The register P1PIN (0xf860) may be read to get the current pin state. Reading this register returns the current pin
value, regardless of the pin’s mode and direction.
Address Range
Device
Chip Select
0x38C - 38D
Neuron Chip
CS1
0x38E-38F
Network Address (redundantly mapped)
CS3
0x390-39F
RTC
CS2
Table 2.1:
CA386-N1 I/O Address Map
Desired Pin Configuration
Desired Pin State
P1DIR
P1LTC
High-impedance input
high impedance
1
1
Open-drain output
high impedance
1
1
Open-drain output
0
1
0
Complementary output
1
0
1
Complementary output
0
0
0
Table 2.2:
Digital I/O Pin Configurations
Summary of Contents for CA386-N1
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