GR-CPCI-GR740-QSG
June 2017, Version 1.4
24
www.cobham.com/gaisler
For the other IOs you will have to make a system-level decision as to whether you can tolerate some IO interfaces
toggling during boot-up, and if not, you could use one of the GPIOs to drive an enable signal to those IO interfaces
transceivers to disable them during boot. Please note that this is not supported currently on the GR-CPCI-GR740
development board.
6.11. Can't boot
First, check that the BREAK button is not asserted (should be in the rightmost position). Second, check that
your boot image is properly loaded into the flash memory (starting address 0xc0000000). You can use the verify
command of GRMON2 that will do it for you. Third, make sure that both memory controllers (mctrl0 and sdctrl0)
are properly initialized. To check if that is happening, you can connect with GRMON2 with no initialization flag (-
ni) once your system has been powered up. For instance, using JTAG/FTDI debug link, the command is "grmon -
ftdi -ni". Please note, that if you use GRMON2 without the "ni" flag, GRMON2 initializes both memory controllers
and thus, the state left by your boot code cannot be analysed. Once in grmon, check the value of the memory
controller configuration registers, as shown below:
grmon2> info reg -v mctrl0
Memory controller with EDAC
0xff903000 Memory config register 1 0x0803c0ff
30 pbrdy 0x0 PROM area bus ready enable
29 abrdy 0x0 Asynchronous bus ready enable
28:27 iobusw 0x1 I/O bus width
26 ibrdy 0x0 I/O bus ready enable
25 bexcn 0x0 Bus error enable
23:20 iows 0x0 I/O wait states
19 ioen 0x0 I/O enable
17:14 prombanksz 0xf PROM bank size
11 pwen 0x0 PROM write enable
9:8 promwidth 0x0 PROM width
7:4 promwws 0xf PROM write wait states
3:0 promrws 0xf PROM read wait states
0xff903004 Memory config register 2 0x00000020
31 sdramrf 0x0 SDRAM refresh enable
30 sdramtrp 0x0 SDRAM TRP parameter
29:27 sdramtrfc 0x0 SDRAM TRFC parameter
26 sdramtcas 0x0 SDRAM TCAS parameter
25:23 sdrambanksz 0x0 SDRAM bank size
22:21 sdramcolsz 0x0 SDRAM column size
20:19 sdramcmd 0x0 SDRAM command
18 d64 0x0 SDRAM 64-bit data bus
17 sdpb 0x0 SDRAM page burst
14 se 0x0 SDRAM enable
13 si 0x0 SRAM disable
12:9 rambanksz 0x0 RAM bank size
7 rbrdy 0x0 RAM bus read enable
6 rmw 0x0 Read-modify-write enable
5:4 ramwidth 0x2 RAM width
3:2 ramwws 0x0 RAM write wait states
1:0 ramrws 0x0 RAM read wait states
0xff903008 Memory config register 3 0x08000000
28 rse 0x0 Reed-Solomon EDAC enable
27 me 0x1 Memory EDAC available
26:12 sdramreload 0x0 SDRAM refresh counter reload value
11 wb 0x0 EDAC diagnostic write bypass enable
10 rb 0x0 EDAC diagnostic read bypass enable
9 re 0x0 RAM EDAC enable
8 pe 0x0 PROM EDAC enable
7:0 tcb 0x0 Test checkbits
0xff903010 Memory config register 5 0x00000000
29:23 iohws 0x0 IO lead out
13:7 romhws 0x0 ROM lead out
0xff903014 Memory config register 6 0x00000000
13:7 ramhws 0x0 RAM lead out
0xff903018 Memory config register 7 0x00000000
31:16 brdyncnt 0x0 Bus ready count
15:0 brdynrld 0x0 Bus ready reload value
grmon2> info reg -v sdctrl0
PC133 SDRAM Controller
0xffe00000 SDRAM config register 0xfea087a4
31 refresh 0x1 SDRAM refresh enable