Cypress FM33256B Manual Download

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FM33256B

Document Number: 001-86213 Rev. *C

Page 6 of 39

The watchdog also incorporates a window timer feature that
allows a delayed start. The starting time and ending time defines
the window and each may be set independently. The starting
time has 25 ms resolution and 0 ms to 775 ms range.

The watchdog EndTime value is located in register 0Ch, bits 4:0,
the watchdog enable is bit 7. The watchdog is restarted by writing
the pattern 1010b to the lower nibble of register 0Ah. Writing the
correct pattern will also cause the timer to load new timeout
values. Writing other patterns to this address will not affect its
operation. Note the watchdog timer is free-running. Prior to
enabling it, users should restart the timer as described above.
This assures that the full timeout is provided immediately after
enabling. The watchdog is disabled when V

drops below V

Note

setting the EndTime timeout setting to all zeroes (00000b)

disables the timer to save power. The listing below summarizes
the watchdog bits.

The programmed StartTime value is a guaranteed maximum
time while the EndTime value is a guaranteed minimum time,
and both vary with temperature and V

voltage. The watchdog

has two additional controls associated with its operation. The
nonvolatile enable bit WDE allows the RST to go active if the
watchdog reaches the timeout without being restarted. If a reset
occurs, the timer will restart on the rising edge of the reset pulse.
If WDE is not enabled, the watchdog timer still runs but has no
effect on RST. The second control is a nibble that restarts the
timer, thus preventing a reset. The timer should be restarted after
changing the timeout value.

This procedure must be followed to properly load the watchdog
registers:

The restart command in step 3 must be issued before t

DOG2

which was programmed in step 2. The window timer starts
counting when the restart command is issued.

Manual Reset

The RST is a bi-directional signal allowing the FM33256B to filter
and de-bounce a manual reset switch. The RST input detects an
external low condition and responds by driving the RST signal
LOW for 100 ms (max). This effectively filters and de-bounces a
reset switch. After this timeout (t

RPU

), the user may continue

pulling down on the RST pin, but SPI commands will not be
locked out.

Note

The internal weak pull-up eliminates the need for additional

external components.

Reset Flags

In case of a reset condition, a flag bit will be set to indicate the
source of the reset. A low-V

reset is indicated by the POR flag,

register 09h bit 5. There are two watchdog reset flags - one for
an early fault (EWDF) and the other for a late fault (LWDF),
located in register 09h bits 7 and 6. A manual reset will result in
no flag being set, so the absence of a flag is a manual reset. Note
that the bits are set in response to reset sources but they must
be cleared by the user. It is possible to read the register and have
both sources indicated if both have occurred since the user
cleared them.

Power Fail Comparator

An analog comparator compares the PFI input pin to an onboard
1.5 V reference. When the PFI input voltage drops below this
threshold, the comparator will drive the PFO pin to a LOW state.
The comparator has 100 mV of hysteresis (rising voltage only) to
reduce noise sensitivity. The most common application of this
comparator is to create an early warning power fail interrupt
(NMI). This can be accomplished by connecting the PFI pin to an
upstream power supply via a resistor divider. An application
circuit is shown below. The comparator is a general purpose
device and its application is not limited to the NMI function.

Figure 4. Window Timer

Watchdog Start Time

WDST(4:0)

0Bh, bits 4:0

Watchdog EndTime

WDET(4:0)

0Ch, bits 4:0

Watchdog Enable

WDE

0Ch, bit 7

Watchdog Restart

WR(3:0)