State Machine Signals
Port
Pin
Name
Description
A5
2
smCYCLE*
Low to start a single 8080 machine cycle. Must hold low at least 500ns to ensure phi2 edge has occurred.
Must return high within 1500ns max. Recommend 750ns low to cycle the processor one cycle.
A4
3
smRESET
High to assert bus PRESET* signal (processor reset). Synced with the rising edge of phi2 to meet the
undocumented 8080 reset timing requirement provided by the 8224
A3
4
smPOC*
POC (Power On Clear) signal from the bus
C5
5
smDATAOE
High to enable output of the CPU inject latch directly to the 8080's data pins
C4
6
smRUN/STOP*
High to let the 8080 run, low to stop the 8080
C3
7
smFFOUT
Positive pulse (<500ns) when OUT to 0FFh performed by 8080
C6
8
smFFIN
Positive pulse (<500ns) when IN from 0FFh performed by 8080
C7
9
smMWRITE
Pulse high to assert bus MWRITE signal and deposit the value from the CPU inject latch into memory
The original front panel asserts this for about 8.5us
B7
10
smDI/LATFF*
High to display data input bus on data LEDs, low to display OUT 0FFh latch on data LEDs
B6
11
smOUTLAT
Pulse high to latch shift register parallel outputs into the CPU inject latch
B5
12
smUNPROT*
Low to assert bus UNPROT signal (memory unprotect)
B4
13
smSEROUT
Serial data output to shift register to update the CPU inject latch. 74LS164 data loads on rising edge
C2
14
smPROT*
Low to assert bus PROT signal (memory protect)
C1
15
smSS*
Low to assert bus SS (single step) to properly enable input buffers on the CPU board during single step
C0
16
smEXTCLR
High to assert bus EXT CLR* signal (external clear)
A2
17
smSERCLK
Serial clock to data shift registers
A1
18
smSERIN
Serial data input from shift registers (front panel switches and value on data LEDs). 74LS165 changes on rise, so read on falling
A0
19
smINLAT*
Pulse low to latch parallel data (front panel switches and value on data LEDs) into serial input shift registers
Port A
7
6
5
4
3
2
1
0
Signal
-
-
smCYCLE*
smRESET
smPOC*
smSERCLK
smSERIN
smINLAT*
Init Value
0
0
1
1
Input
0
Input
1
0x31
Tristate
0
0
0
0
1
0
1
0
0x0A
Port B
7
6
5
4
3
2
1
0
Signal
smDI/LATFF*
smOUTLAT
smUNPROT*
smSEROUT
-
-
-
-
Init Value
1
0
1
0
0
0
0
0
0xA0
Tristate
0
0
0
0
0
0
0
0
0x00
Port C
7
6
5
4
3
2
1
0
Signal
smMWRITE
smFFIN
smDATAOE
smRUN/STOP*
smFFOUT
smPROT*
smSS*
smEXTCLR
Init Value
0
Input
0
0
Input
1
1
0
0x06
Tristate
0
1
0
0
1
0
0
0
0x48
