Digital Equipment PDF-10, System Reference Manual

Page 1: ...gpgMHittKMtfttlitfg ORDER NO DEC 10 HGAA D FROM PROGRAM LIBRARY MAYNARD MASSACHUSETTS PRICE 5 00 DIRECT COMMENTS CONCERNING THIS MANUAL TO SOFTWARE QUALITY CONTROL MAYNARD MASSACHUSETTS DIGITAL EQUIPM...

Page 2: ...1968 by Digital Equipment Corporation Instruction times operating speeds and the like are included here for reference only they are not to be taken as specifications Written and designed for Digital E...

Page 3: ...2 10 Pushdown list 2 12 2 3 Byte Manipulation 2 15 2 4 Logic 2 17 Shift and rotate 2 24 2 5 Fixed Point Arithmetic 2 26 Arithmetic shifting 2 3 1 2 6 Floating Point Arithmetic 2 32 Scaling 2 33 Opera...

Page 4: ...T EQUIPMENT 3 1 3 1 Paper Tape Reader 3 1 Readin mode 3 4 3 2 Paper Tape Punch 3 5 3 3 Teletype 3 7 APPENDICES A Instruction and Device Mnemonics A 1 Numeric listing A3 Alphabetic listing A6 Device mn...

Page 5: ...of bits within a word Registers that hold addresses have eighteen bits numbered 18 35 according to the position of the address in a word Words are used either as computer instructions in the program a...

Page 6: ...ny memory location stop or interrupt the program whenever a particular location is referenced and through AS the operator can supply a starting address for the program Through the memory indicators MI...

Page 7: ...th Every instruction has a 4 bit index register address field which can address fifteen of these locations for use as index registers in modifying the 18 bit memory address a zero index register addre...

Page 8: ...s are the magnitude in ordinary binary notation The negative of a number is obtained by taking its twos complement If x is an digit binary number its twos complement is 2 x and its ones complement is...

Page 9: ...left in these two cases the range of numbers repre sented by a single word is 235 to 2 35 1 or 1 to 1 2 35 Since multiplica tion and division make use of double length numbers there are special instru...

Page 10: ...ution about truncation given for fixed point multiplication applies to all floating point operations as they all produce extra length results but here the programmer may request rounding which automat...

Page 11: ...e actual address used to fetch the operand or alter program flow Bit 13 specifies the type of addressing bits 14 17 spec ify an index register for use in address modification and the remaining eightee...

Page 12: ...ulation is carried out for every instruction regardless of the type of infor mation that must be specified for its execution or even if the result is ignored In the discussion of any instruction E ref...

Page 13: ...t memories by taking instructions from one memory and data from another The hardware also allows pairs of memories to be interleaved in such a way that consecutive addresses actually alternate between...

Page 14: ...e nine or thirteen bits Eg the mnemonic MOVNS assembles as 213000 000000 and MOVNS 2570 assembles as 213000 002570 This latter word when executed as an instruc tion produces the twos complement negati...

Page 15: ...however available for all standard device codes To control the priority interrupt system whose code is 004 one may give CONO 4 1302 which assembles as 700600 0001302 or equivalently CONO PI 1302 The...

Page 16: ......

Page 17: ...or execution time for each instruction is also given at the top unless the time differs from one mode to another The time listed is that required for direct addressing without indexing ie with no effe...

Page 18: ...more complex examples using a variety of instructions are given in 2 1 1 2 1 HALF WORD DATA TRANSMISSION These instructions move a half word and may modify the contents of the other half of the destin...

Page 19: ...2 1 HALF WORD DATA TRANSMISSION 2 3 An additional letter may be appended to indicate the mode which deter mines the source and destination of the half word moved Mode...

Page 20: ...2 4 HLLOI sets AC to all Os in the left half all Is in the right HLLO CENTRAL PROCESSOR Half Word Left to Left Ones 2 1 520...

Page 21: ...2 1 HALF WORD DATA TRANSMISSION 2 5 H R LM Half Right to Left Memory H R LS Half Right to Left Self 506 2 90 3 01 MS 507 2 76 2 87 jus HRLZ Half Word Right to Left Zeros 5 14...

Page 22: ...al contents of the destination are lost H R L E Half Right to Left Extend HRLEI Half Right to Left Extend Immediate H R LEM Half Right to Left Extend Memory HRLES Half Right to Left Extend Self 534 2...

Page 23: ...2 1 HALF WORD DATA TRANSMISSION 2 7 HRRO Half Word Right to Right Ones 560...

Page 24: ...CENTRAL PROCESSOR HLRM Half Left to Right Memory HLRS Half Left to Right Self 2 1 546 547 2 90 3 01 2 76 2 87 HLRZI merely clears AC and is thus equivalent to HLLZI HLRZ Half Word Left to Right Zeros...

Page 25: ...he symbol XR as an octal number between 1 and 17 Suppose that at some point we wish to use the two halves of XR inde pendently as operands taken as 18 bit positive numbers for computations We can begi...

Page 26: ...r and type of trans fers Assuming at least one word is moved a BLT takes 97 1 08 MS plus 2 26 2 48 jus per transfer from fast memory to core and 2 61 2 83 us per transfer from core to fast memory or f...

Page 27: ...fix I M S Source E The word 0 AC E Destination AC AC E E but also AC if A is nonzero Keeping instructions and op erands in different memories saves 47 36 is in memory mode 20 09 MS in self mode When E...

Page 28: ...ized number If the source word is zero set Carry and Carry 1 The source is unaffected the original contents of the destination are lost MOVN Move Negative MOVNI Move Negative Immediate MOVNM Move Nega...

Page 29: ...2 2 FULL WORD DATA TRANSMISSION 2 13 two subroutine calling instructions that utilize a pushdown list of jump ad dresses 2 9 PUSH Push Down 3 85 4 07 261...

Page 30: ...ns beginning at that point In the POP 10 the pushdown list is kept in a random access core mem ory so the restrictions on order of entry and removal of items actually apply only to the standard addres...

Page 31: ...akes a byte from the right end of AC and inserts it at any desired position in the memory location a load instruction takes a byte from any position in the memory location and places it right justifie...

Page 32: ...2 16 CENTRAL PROCESSOR 2 3 Keeping the pointer in fast memory saves 34 jus Taking bytes from a fast memory location saves another 34 us LDB Load Byte 4 02 4 35 A5 P S 26 us 135...

Page 33: ...36 no byte is processed loading merely clears AC If both P and S are less than 36 but P S 36 a byte of size 36 P is loaded from position P or the right 36 P bits of the byte are deposited in position...

Page 34: ...oth merely clear AC MACRO also recognizes CLEAR CLEARI CLEARM and CLEARS as equivalent to the set to zeros mnemonics For an instruction without an operand one that merely clears a location or sets it...

Page 35: ...2 4 SETCA LOGIC Set to Complement of AC 450...

Page 36: ...2 20 CENTRAL PROCESSOR 2 4 AND And with AC 404...

Page 37: ...2 4 ANDCB LOGIC And Complements of Both 440...

Page 38: ...2 22 CENTRAL PROCESSOR 2 4 ORCM Inclusive Or Complement of Memory with AC 464...

Page 39: ...46 2 90 3 01 us EQVB Equivalence to Both 447 2 90 3 01 jus The original contents of the destination can be recovered except in EQVB where both operands are replaced by the result In the other three mo...

Page 40: ...tructions shift or rotate right or left the contents of AC or the contents of two accumulators A and A l mod 208 concat enated into a 72 bit register with A on the left The illustration below shows th...

Page 41: ...s specified by the result of the effective address calculation taken as a signed number in twos complement notation modulo 2 8 in magnitude In other words the effective shift E is the number composed...

Page 42: ...2 26 CENTRAL PROCESSOR i2 5 ROTC Rotate Combined Left 2 00 2 11 15 us Right 1 84 1 95 15 jus 245...

Page 43: ...ion if they are to give meaningful information about the instruction afterward However the program can check the flags following a series of instructions to determine whether the entire series was fre...

Page 44: ...54 43 us less Keeping instructions and op erands in different memories saves 47 36 jus in MULM 31 20 MS in MULB When E addresses a fast memory location MUL takes 34 us less than the time given MULM t...

Page 45: ...the multiplication algorithm Minimum times with a zero multiplier are IMUL IMULI IMULM IMULB 8 42 8 64 MS 7 57 7 68 MS 9 39 9 61 MS 9 39 9 61 MS These must be increased by 13 MS for each transition T...

Page 46: ...epresent the bits of the character Assum ing the character is right justified in AC we first duplicate it twice to the left producing abc def gha bed efg hob cde fgh where the bits in positions 12 35...

Page 47: ...ts are brought in at the end being vacated a left shift brings in Os at the right whereas a right shift brings in the equivalent of the sign bit at the left In either case information shifted out at t...

Page 48: ...2 32 CENTRAL PROCESSOR 2 6 ASHC Arithmetic Shift Combined Left Right...

Page 49: ...ns because of extreme loss of significance eg adding X 2 2 and X 269 gives a zero result as the first operand having a smaller exponent looks smaller to the processor and is shifted to oblivion A numb...

Page 50: ...can be used to float a fixed number with 27 or fewer significant bits To float an integer contained within AC bits 9 35 FSC AC 233 inserts the correct exponent to move the binary point from the right...

Page 51: ...ow If the exponent is 127 set Overflow and Floating Overflow the result stored has an expo nent 256 less than the correct one If 128 set Overflow Floating Over flow and Floating Underflow the result s...

Page 52: ...of normalized operands requires at most one normali zation step for the result If unnormalized operands are used all times must be in creased by 25 V FMPR CENTRAL PROCESSOR Floating Multiply and Round...

Page 53: ...divi sion is not performed only 3 5 4 us are required Operations without Rounding Instructions that do not round are faster for processing floating point num bers with fractions containing fewer than...

Page 54: ...oating point instructions perform the four standard arith metic operations with normalization but without rounding All use AC and the contents of location E as operands and have four modes Mode Basic...

Page 55: ...of the fraction is zero clear AC A Otherwise place a low order word for a double length result in A l by putting a in bit 0 an exponent in positive form 27 less than the exponent of the sum in bits 1...

Page 56: ...0 CENTRAL PROCESSOR 2 6 FMP Use of normalized operands requires at most one normali zation step for the result If unnormalized operands are used all times must be in creased by 25N Floating Multiply 1...

Page 57: ...idend otherwise it is 27 less If the remainder exponent is 1 27 or 1 28 or the fraction is zero clear AC A 1 Otherwise place the floating point remainder exponent and frac tion with the sign of the di...

Page 58: ...s all entries accounted for The eight remaining instructions jump or skip if the operand or operands satisfy a test condition specified by the mode Mode Suffix Never Less L Equal E Less or Equal LE Al...

Page 59: ...2 7 ARITHMETIC TESTING 2 43 CAI...

Page 60: ...r than Zero 323 324 325 326 327 When E addresses a fast mem ory location this instruction takes 34 us less than the time given If A is zero SKIP is a no op otherwise it is equivalent to MOVE Instructi...

Page 61: ...2 7 ARITHMETIC TESTING 2 45 AOS Add One to Memory and Skip if Condition Satisfied 2 94 3 05 jus 35...

Page 62: ...g the count in fast memory saves 54 43 us keeping it in a different mem ory from the instruction saves 20 09 MS CENTRAL PROCESSOR SOS Subtract One from Memory and Skip if Condition Satisfied 2 7 2 94...

Page 63: ...d bit positions Complements all masked bits Places Is in all masked bit positions An additional letter may be appended to indicate the mode which spec ifies the condition the masked bits must satisfy...

Page 64: ...2 48 TRN is a no op CENTRAL PROCESSOR TRN Test Right No Modification and Skip if Condition Satisfied 2 8 1 85 1 96 jus 60...

Page 65: ...2 8 LOGICAL TESTING AND MODIFICATION 2 49 TRO Test Right Ones and Skip if Condition Satisfied 1 85 1 96 jus 66...

Page 66: ...2 50 CENTRAL PROCESSOR 2 TLC Test Left Complement and Skip if Condition Satisfied 1 85 1 96 jus 64...

Page 67: ...2 8 LOGICAL TESTING AND MODIFICATION 2 51 TDZ Test Direct Zeros and Skip if Condition Satisfied 2 70 2 92 MS 63...

Page 68: ...2 52 TSN is a no op that refer ences memory CENTRAL PROCESSOR TSN Test Swapped No Modification and Skip if Condition Satisfied 2 8 2 70 2 92 MS 61...

Page 69: ...TING AND MODIFICATION 2 53 TSCA Test Swapped Complement but Always Skip TSCN Test Swapped Complement and Skip if Not All Masked Bits Equaled 655 657 ISO Test Swapped Ones and Skip if Condition Satisfi...

Page 70: ...ops when run on a computer that contains no special hardware for them but for program compatibility it is advised that they not be used regularly as no ops The present section treats all program cont...

Page 71: ...erflow to be set and indicates that one of the following has occurred An ADDA has added two positive numbers with sum 2 35 An SUBAf has subtracted a negative number from a positive num ber with differ...

Page 72: ...instruction other than DFN the exponent of the result was 128 and Overflow and Floating Overflow have been set 12 No Divide any of the following has set Overflow In a DIVX the dividend was greater th...

Page 73: ...sequential operation from there In either case AC is unaffected the original contents of AC 4 1 are lost Note that when AC is nega tive the second accumulator is cleared just as it would be if AC wer...

Page 74: ...2 58 CENTRAL PROCESSOR 2 9 JSP Jump and Save PC 1 36 1 47 us 265...

Page 75: ...was stored in AC as in a JSP a common procedure is to use AC to index a zero address eg JRSTF AC so its right half becomes the effec tive Gump address If the PC word was stored in core as in a JSR on...

Page 76: ...s entry point reserved for the PC word Hence it is nonreentrant the JSR modifies memory so the subroutine cannot be shared with other programs The JSP requires an accumulator but it is faster and is c...

Page 77: ...H 1 T JRST PRINT 1 PROGRAM CONTROL Initialize left half of pointer Increment pointer and load byte Upon reaching zero character return to one beyond last data word Print routine Get next character 2 6...

Page 78: ...PC in the left and right of AC 17 saves the previous contents of AC 17 in the first subroutine location and jumps to E 1 To return to the next higher level a JRA restores the previous contents of AC...

Page 79: ...2 9 POPJ PROGRAM CONTROL Pop Up and Jump 2 96 3 18 263...

Page 80: ...r operations wherein the word given as an instruction is trapped and must be interpreted by a routine included for this purpose by the programmer In time sharing however half of the codes are set asid...

Page 81: ...lost is in T the count is kept in CNT and the mask created in each step is stored in TEMP MOVEI CNT 0 ClearCNT MOVN TEMP T Make mask to select rightmost 1 TDZE T TEMP Clear rightmost 1 in T AOJA CNT...

Page 82: ...searching for information in tables and lists of all kinds Suppose we wish to find a particular item in a table beginning at location TAB and containing N items Accumulator T contains the item The ri...

Page 83: ...length of the list in accumulator CNT MOVEI CNT 0 ClearCNT JUMPE T OUT Jump out if T contains HRRZ T T Get next address AOJA CNT 2 Count and go back I A rVt A AH Ad Double Precision Floating Point The...

Page 84: ...2 68 CENTRAL PROCESSOR 12 12 DFDV FDVL...

Page 85: ...2 12 COM INPUT OUTPUT Conditions In 4 87 4 98 jus 7...

Page 86: ...2 70 CONSO CENTRAL PROCESSOR Conditions In and Skip if One 2 12 4 11 4 22 jus 7...

Page 87: ...ection network decodes bits 3 9 of the instruction so that only the addressed device responds to signals sent by the processor over the in out bus To use the device with the priority interrupt the pro...

Page 88: ...top it after the final DATAI Other devices operate in one or the other of these two ways but differ in various respects The tape punch and teletype output are like the reader Teletype input is initiat...

Page 89: ...in memory including fast memory except in location 0 The operation affects none of memory except location and the block area Upon completing the block the processor halts only if the single instruc ti...

Page 90: ...ions no longer hold A single channel will shut out all others of lower priority if every time its service routine dismisses the interrupt a device assigned to it is already waiting with another reques...

Page 91: ...sophisticated programs 4 Block or Data IO Instructions One or the other of two actions can result from executing one of these as an interrupt instruction If the instruction in 40 27V is a BLKI or BLKO...

Page 92: ...the left half of the PC word if the routine was called by a JSR JSP or PUSHJ 2 9 If flag restoration is not desired a JRST 10 can be used instead CAUTION An interrupt routine must dismiss the interrup...

Page 93: ...the channels selected by Is in bits 29 35 so interrupt requests cannot be accepted on them unless made by a CONO PI with a 1 in bit 24 27 Deactivate the priority interrupt system The processor can th...

Page 94: ...ter a second time This means that the interrupt routine must check the flag before using the same pointer as it now points to the next byte Giving an ILDB or IDPB would skip a byte And if the routine...

Page 95: ...andled by the condition IO instructions that address the priority interrupt system 2 13 The remaining flags are handled by condition instructions that address the processor Its device code is 000 mnem...

Page 96: ...outside of its assigned area and the user instruction was ter minated at that time The setting of this flag requests an interrupt at which time PC points either to the instruction that caused the vio...

Page 97: ...ters that have been typed in at the keyboard This device has the slowest transfer rate of any but it provides a convenient means of man machine interaction 3 1 PAPER TAPE READER The reader processes...

Page 98: ...3 2 BASIC IN OUT EQUIPMENT CONI PTR Conditions In Paper Tape Reader 3 1 71064...

Page 99: ...needed Wait if necessary DONE CONO PTR 0 TRO F 1 JEN DONE Interrupt routine block done Stop tape Set F bit 35 Dismiss and restore flags Operation Tapes must be unoiled and opaque The reader is locate...

Page 100: ...he tape contains any number of data blocks and ends with a transfer block Each data block contains any number of words of program data preceded by a standard IO block pointer for the data only and fol...

Page 101: ...s per second It can operate in alphanumeric or binary mode as specified by the or 1 state respectively of the Binary flag but in either mode a single tape moving command punches only one line Alphanum...

Page 102: ...3 6 BASIC IN OUT EQUIPMENT DATAO FTP Data Out Paper Tape Punch 3 2 71014...

Page 103: ...eing loaded To remove a length of perforated tape from the bin first press the feed button long enough to provide an adequate trailer at the end of the tape and also leader at the beginning of the nex...

Page 104: ...control code with incorrect parity The Model 37 has the entire character set listed in the table in Appendix B Lower case characters are not available on the Model 35 but transmitting a lower case co...

Page 105: ...3 3 TELETYPE 3 9 DATAI TTY Data In Teletype 71204...

Page 106: ...ces the paper vertically at six lines to the inch and must be combined with a return to start a new line The local advance feed and return keys affect the printer directly and do not transmit codes Ap...

Page 107: ...ter and receiver The remaining lights display the PI assignment and flags the Input and Output Done flags are labeled TTI FLAG and TTO FLAG Teletype manuals supplied with the equipment give complete i...

Page 108: ...obvious observe the paper or ribbon path and duplicate it The other tasks are usually left for maintenance personnel In any event the best and easiest way to learn to do any of these things is to have...

Page 109: ...Appendices...

Page 110: ......

Page 111: ...or user mode an asterisk indicates a UUO mnemonic recognized by MACRO for communication with the PDF 10 Time Sharing Monitor All UUOs 000 077 are identical when the processor is not in user mode In ou...

Page 112: ...A2 MNEMONICS E...

Page 113: ...057 060 061 062 062 063 064 065 066 067 070 071 072 073 074 075 076 077 100 127 130 131 ILLEGAL USER UUO S CALL INIT RESERVED FOR SPECIAL MONITORS CALLI OPEN RESERVED FOR DEC RENAME IN OUT SETSTS STA...

Page 114: ...A4 MNEMONICS 25510...

Page 115: ...NUMERIC LISTING A5 465...

Page 116: ...1 442 420 423 421 422 405 406 253 252 340 344 342 347 345 341 343 346 350 354 352 357 355 351 353 356 000 240 244 70000 70010 BLT CAI CAIA CAIE CAIG CAIGE CAIL CAILE CAIN CALL CALLI CAM CAMA CAME CAMG...

Page 117: ...ALPHABETIC LISTING A7 FSC...

Page 118: ...AI SETAM SETCA SETCAB SETCAI SETCAM SETCM SETCMB SETCMI SETCMM SETM SETMB SETMI SETMM SETO SETOB SETOI SETOM SETSTS SETZ SETZB SETZI SETZM SKIP 472 464 467 465 466 435 436 057 065 067 004 140 262 263...

Page 119: ...ALPHABETIC LISTING A9 USETI 074 tUTS 214 XORB 433 USETO 075 XCT 256 XORI 431 fUTC 210 XOR 430 XORM 432...

Page 120: ...A10 MNEMONICS...

Page 121: ...the delete code Hence a character hidden under DEL is printed by sending the printer two 1 77s in a row Besides printing characters the line printer responds to ten control charac ters HT CR LF VT FF...

Page 122: ...rtical tab VTAB Control K on Model 35 014 FF Form feed to top of next page PAGE Control L 1 015 CR Carriage return to beginning of line Control M on Model 35 1 016 SO Shift out changes ribbon color to...

Page 123: ...TELETYPE CODE B3 Even Parity Bit...

Page 124: ...B4 INPUT OUTPUT CODES Even Parity Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1...

Page 125: ...TELETYPE CODE B5 Even...

Page 126: ...B6 INPUT OUTPUT CODES CARD CODES PDF 10...

Page 127: ...CARD CODES B7 Column...

Page 128: ...C 029 t End of File End of File Mode Switch Mode Switch Binary Binary Octal 4006 2202 2102 2042 2022 2012 2006 1202 1102 1042 1022 1012 1006 7400 5252 NOTE There is a single key for the 082 punch on t...

Page 129: ...APPENDIX C MISCELLANY Instruction Flow Simplified C2 Word Formats C3 Instruction Timing Flow Chart C4 In out Device Bit Assignments C6 Indicator Panels Cg Powers of Two CIO Cl...

Page 130: ...2 MISCELLANY INSTRUCTION FETCH INTERRUPT REQUEST BYT INSTR CALCULATION BLKI BLKO DATA FETCH POINTER DONE IN INTERRUPT REQUEST INSTRUCTION EXECUTION BYTE BLKI BLK DATA STORE INSTRUCTION FLOW SIMPLIFIED...

Page 131: ...WORD FORMATS C3 BASIC INSTRUCTIONS INSTRUCTION CODE INCLUDING MODE...

Page 132: ...C4 MISCELLANY 10 L IF IN USER MODE INSTRUCTION TIMING FLOW CHART...

Page 133: ...INSTRUCTION TIMING C5 INSTRUCTION EXECUTION t...

Page 134: ...C6 MISCELLANY n S ri nm SiS5 fe tu 3s tat i S 5 J p Sp Jp dim Sa...

Page 135: ...IN OUT DEVICE BIT ASSIGNMENTS C7...

Page 136: ...C8 MISCELLANY N ed M o o 03 O o o s OH O s 4 c C3 c 03 CJ 3 c OH O...

Page 137: ...INDICATOR PANELS C9 a o o o 6 o o u n a T3 C 05 m VO O E v O o 03 o O...

Page 138: ...56 839 400 250 464 677 810 668 945 312 5 1 125 899 906 842 624 50 0 000 000 000 000 000 888 178 419 700 125 232 338 905 334 472 656 25 2 251 799 813 685 248 51 0 000 000 000 000 000 444 089 209 850 06...