9.7
General-purpose digital I/O
dimtel
dimtel
9.6
ECL delay lines
Several MC100EP195 ECL delay lines are used on the iGp-5120F to line up
the received RF clock and the fiducial signal. These lines are controlled by
registers described in Table 15.
Delay line 0 controls the delay of the ADC clock. Relative delay between
lines 1 and 2 is used to achieve reliable detection of the fiducial falling edge
in the front-end. Once that relative delay is determined, both 1 and 2 must
be adjusted together to achieve proper timing between the fiducial (reset)
pulse to the ADC and the ADC clock. This second stage fixes relative delays
between 0, 1, and 2. Finally, delay line 3 must be adjusted to achieve optimal
placement of the DAC clock relative to the FPGA data.
Table 15: FPGA registers: ECL delay lines
Address
Bits
Definition
0x000130
9:0
Delay line 0 (ADC clock)
0x000131
9:0
Delay line 1 (Fiducial clock)
0x000132
9:0
Delay line 2 (Fiducial)
0x000133
9:0
Delay line 3 (DAC clock)
9.7
General-purpose digital I/O
There are two distinctly different drivers implemented in the gateware for the
control of the general-purpose digital I/O port of the iGp-5120F. A generic
bit-by-bit driver is accessed when bit 16 of the main control register (0x100)
is set to 0. The port is accessed via three registers listed in Table 16.
Table 16: FPGA registers: bit-by-bit GPIO
Address
Bits
Definition
0x000138
31:0
Output data
0x000139
31:0
Direction (1 - out, 0 - in)
0x00013a
31:0
Pin value readback
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