HOST INTERFACE (HI)
MOTOROLA
PORT B
5 - 37
5.3.5.4
Servicing Non-DMA Interrupts
When HM0=HM1=0 (non-DMA) and HREQ is connected to the host processor interrupt
input, the HI can request service from the host processor by asserting HREQ. In the non-
DMA mode, HREQ will be asserted when TXDE=1 and/or RXDF=1 and the correspond-
ing mask bit (TREQ or RREQ, respectively) is set. This is depicted in Figure 5-17.
Generally, servicing the interrupt starts with reading the ISR, as described in the previous
section on polling, to determine which DSP has generated the interrupt and why. When
multiple DSPs occur in a system, the HREQ bit in the ISR will normally be read first to
determine the interrupting device. The host processor interrupt service routine must read
or write the appropriate HI register to clear the interrupt. HREQ is deasserted when the
enabled request is cleared or masked.
In the case where the host processor is a member of the MC680XX Family, servicing the
interrupt will start by asserting HREQ to interrupt the processor (see Figure 5-17). The
host processor then acknowledges the interrupt by asserting HACK. While HREQ and
HACK are simultaneously asserted, the contents of the IVR are placed on the host data
bus. This vector will tell the host processor which routine to use to service the HREQ
interrupt.
The HREQ pin is an open-drain output pin so that it can be wire-ORed with the HREQ pins
from other DSP56002 processors in the system. When the DSP56002 generates an inter-
rupt request, the host processor can poll the HREQ bit in each of the ISRs to determine
which device generated the interrupt.
7
0
HREQ
DMA
0
HF3
HF2
TRDY
TXDE
RXDF
STATUS
ISR
INIT
HM1
HM0
HF1
HF0
0
TREQ
RREQ
7
0
$3
$2
ICR
MASK
EXCEPTION SOURCE
HREQ ASSERTED
HREQ
Figure 5-17 HI Interrupt Structure
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
.
..
