BUS CONTROL REGISTER (BCR)
4 - 14
PORT A
MOTOROLA
Figure 4-9 illustrates which of the four BCR subregisters affect which external memory
space. All the internal peripheral devices are memory mapped, and their control registers
reside between X:$FFC0 and X:$FFFF.
To load the BCR the way it is shown in Figure 4-8, execute a “MOVEP #$48AD,
X:$FFFE” instruction. Or, change the individual bits in one of the four subregisters by
using the BSET and BCLR instructions which are detailed in the
DSP56000 Family Man-
ual
,
SECTION 6
and
APPENDIX A
.
Figure 4-8 shows an example of mixing different memory speeds and memory-mapped
peripherals in different address spaces. The internal memory uses no wait states, X: mem-
ory uses two wait states, Y: memory uses four wait states, P: memory uses five wait states,
and the analog converters use 14 wait states. Controlling five different devices at five dif-
ferent speeds requires only one additional logic package. Half the gates in that package
are used to map the analog converters to the top 64 memory locations in Y: memory.
BUS CONTROL REGISTER
$FFC0
$FFFF
$FFC0
$FFFE
$FFFF
X:$FFFE
15
12
11
8
7
4
3
0
EXTERNAL
X MEMORY
*
EXTERNAL
Y MEMORY
*
EXTERNAL
P MEMORY
*
EXTERNAL
I/0 MEMORY
*
EXTERNAL
PROGRAM
MEMORY
INTERNAL
PROGRAM
RAM
$FFFF
$200
0
EXTERNAL
X DATA
MEMORY
$200
$100
0
$200
$100
0
EXTERNAL
Y DATA
MEMORY
EXTERNAL
PERIPHERALS
INTERNAL
Y ROM
INTERNAL
Y RAM
INTERNAL
X ROM
INTERNAL
X RAM
PROGRAM
MEMORY SPACE
X DATA
MEMORY
SPACE
Y DATA
MEMORY
SPACE
* Zero to 15 wait states can be inserted into each external memory access.
Figure 4-9 Bus Control Register
ON-CHIP PERIPHERALS
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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