x
x+1
x+2
x+3
next
5..v_wxyz
next
wdata
next
400v_wxyz
400v_wxyz
next
next
5..v_wxyz
wdata bfi rdata
wdata bfi rdata
next
rdata
CYCLE RULER
hclk
BME AHB Input Bus
mx_haddr
mx_hattr
mx_hwrite
mx_hwdata
mx_hrdata
mx_hready
BME AHB Output Bus
sx_haddr
sx_hattr
sx_hwrite
sx_hwdata
sx_hrdata
sx_hready
BME Datapath
control_state_dp1
control_state_dp2
reg_addr_data_dp
Figure 16-2. Decorated store: bit field insert timing diagram
All the decorated store operations follow the same execution template shown in
, a two-cycle read-modify-write operation:
1. Cycle x, 1st AHB address phase: Write from input bus (mx_h<signal>) is translated
into a read operation on the output bus (sx_h<signal>) using the actual memory
address (with the decoration removed) and then captured in a register
(reg_addr_data_dp).
2. Cycle x+1, 2nd AHB address phase: Write access with the registered (but actual)
memory address is output (sx_h<signal>)
3. Cycle x+1, 1st AHB data phase: Memory read data (sx_hrdata) is modified using the
input bus write data (mx_hwdata) and the function defined by the decoration and
captured in a data register. (reg_addr_data_dp); the input bus cycle is stalled
(mx_hready = 0).
4. Cycle x+2, 2nd AHB data phase: Registered write data is sourced onto the output
write data bus (sx_hwdata).
Chapter 16 Bit Manipulation Engine (BME)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
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