• If CR1[SE] = 1, the external SAMPLE input is used as sampling clock
• IF CR1[SE] = 0, the divided bus clock is used as sampling clock
• If enabled, the Filter block will incur up to one bus clock additional latency penalty
on COUT due to the fact that COUT, which is crossing clock domain boundaries,
must be resynchronized to the bus clock.
• CR1[WE] and CR1[SE] are mutually exclusive.
26.7 Memory map/register definitions
CMP memory map
Absolute
address
(hex)
Register name
Width
(in bits)
Access Reset value
Section/
page
4007_3000 CMP Control Register 0 (CMP0_CR0)
8
R/W
00h
4007_3001 CMP Control Register 1 (CMP0_CR1)
8
R/W
00h
4007_3002 CMP Filter Period Register (CMP0_FPR)
8
R/W
00h
4007_3003 CMP Status and Control Register (CMP0_SCR)
8
R/W
00h
4007_3004 DAC Control Register (CMP0_DACCR)
8
R/W
00h
4007_3005 MUX Control Register (CMP0_MUXCR)
8
R/W
00h
26.7.1 CMP Control Register 0 (CMPx_CR0)
Address: 4007_3000h base + 0h offset = 4007_3000h
Bit
7
6
5
4
3
2
1
0
Read
Write
Reset
0
0
0
0
0
0
0
0
CMPx_CR0 field descriptions
Field
Description
7
Reserved
This field is reserved.
This read-only field is reserved and always has the value 0.
6–4
FILTER_CNT
Filter Sample Count
Represents the number of consecutive samples that must agree prior to the comparator ouput filter
accepting a new output state. For information regarding filter programming and latency, see the
.
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not
recommended. If SE = 0, COUT = COUTA.
Table continues on the next page...
Chapter 26 Comparator (CMP)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
387
