The following figure shows the TPM structure. The central component of the TPM is the
16-bit counter with programmable final value and its counting can be up or up-down.
no clock selected
(counter disable)
module clock
external clock
CMOD
synchronizer
CPWMS
PS
TOIE
TOF
MOD
Module counter
timer overflow
interrupt
Channel 0
MS0B:MS0A
ELS0B:ELS0A
input capture
mode logic
channel 0
input
C0V
CH0IE
CH0F
channel 0
interrupt
channel 0
output signal
output modes logic
prescaler
Channel N
MSNB:MSNA
ELSNB:ELSNA
input capture
mode logic
channel N
input
CNV
CHNIE
CHNF
channel N
interrupt
channel N
output signal
output modes logic
(generation of channel N outputs signals in
output compare, EPWM and CPWM modes)
(generation of channel 0 outputs signals in
output compare, EPWM and CPWM modes)
(1, 2, 4, 8, 16, 32, 64 or 128)
3
Figure 27-1. TPM block diagram
27.2 TPM Signal Descriptions
shows the user-accessible signals for the TPM.
Table 27-1. TPM signal descriptions
Signal
Description
I/O
TPM_EXTCLK
External clock. TPM external clock can be selected to increment the TPM
counter on every rising edge synchronized to the counter clock.
I
TPM_CHn
TPM channel (n = 1 to 0)
I/O
Chapter 27 Timer/PWM Module (TPM)
KL02 Sub-Family Reference Manual, Rev. 2.1, July 2013
Freescale Semiconductor, Inc.
411
