Chapter 10 Analog-to-Digital Converter (ADC12B_LBA_V1)
S12ZVHY/S12ZVHL Family Reference Manual Rev. 1.05
Freescale Semiconductor
385
10.4.2.16 ADC Command Register 1 (ADCCMD_1)
A command which contains reserved bit settings causes the error flag CMD_EIF being set and ADC cease
operation.
Read: Anytime
Write: Only writable if bit SMOD_ACC is set
(see also
Section 10.4.2.2, “ADC Control Register 1 (ADCCTL_1)
bit SMOD_ACC description for more
details)
NOTE
If bit SMOD_ACC is set modifying this register must be done carefully -
only when no conversion and conversion sequence is ongoing.
Module Base + 0x0015
23
22
21
20
19
18
17
16
R
VRH_SEL
VRL_SEL
CH_SEL[5:0]
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-19. ADC Command Register 1 (ADCCMD_1)
Table 10-22. ADCCMD_1 Field Descriptions
Field
Description
23
VRH_SEL
Reference High Voltage Select Bit
— This bit selects the high voltage reference for current conversion.
0 VRH_0 input selected as high voltage reference.
1 VRH_1 input selected as high voltage reference.
22
VRL_SEL
Reference Low Voltage Select Bit
— This bit selects the voltage reference for current conversion.
0 VRL_0 input selected as low voltage reference.
1 VRL_1 input selected as low voltage reference.
21-16
CH_SEL[5:0]
ADC Input Channel Select Bits
— These bits select the input channel for the current conversion. See
for channel coding information.
Table 10-23. Analog Input Channel Select
CH_SEL[5]
CH_SEL[4]
CH_SEL[3]
CH_SEL[2]
CH_SEL[1]
CH_SEL[0]
Analog Input Channel
0
0
0
0
0
0
VRL_0/1
0
0
0
0
0
1
VRH_0/1
0
0
0
0
1
0
(VRH_0/1 + VRL_0/1) / 2
0
0
0
0
1
1
Reserved
0
0
0
1
0
0
Reserved
0
0
0
1
0
1
Reserved
0
0
0
1
1
0
Reserved
