MCF52110 ColdFire® Integrated Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
8-1
Preliminary
Chapter 8
Power Management
8.1
Introduction
This chapter explains the low-power operation of the MCF52110.
8.1.1
Features
The following features support low-power operation.
•
Four modes of operation: run, wait, doze, and stop
•
Ability to shut down most peripherals independently
•
Ability to shut down the external CLKOUT pin
8.2
Memory Map/Register Definition
The power management programming model consists of registers from the SCM and CCM memory space,
as shown in
Table 8-1. Power Management Memory Map
IPSBAR
Offset
1
1
Addresses not assigned to a register and undefined register bits are reserved for expansion.
Register
Width
(bits)
Access
Reset Value
Section/Page
0x11_0004
Chip Configuration Register (CCR)
2
2
The CCR is described in the Chip Configuration Module. It is shown here only to warn against accidental writes to this register
when accessing the LPCR.
16
R
0x1
0x11_0007
Low-Power Control Register (LPCR)
8
R/W
0x2
0x00_000C
Peripheral Power Management Register High (PPMRH)
32
R/W
0x0
0x00_0010
Core Reset Status Register (CRSR)
3
8
R/W
0x00_0011
Core Watchdog Control Register (CWCR)
3
8
R/W
0x0
0x00_0012
Low-Power Interrupt Control Register (LPICR)
8
R/W
0x0
0x00_0013
Core Watchdog Service Register (CWSR)
3
8
R/W
0x00_0018
Peripheral Power Management Register Low (PPMRL)
32
R/W
0x1
0x00_0021
Peripheral Power Management Set Register (PPMRS)
8
W
0x0
0x00_0022
Peripheral Power Management Clear Register (PPMRC)
32
R/W
0x0
