Power Management
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
9-7
9.2.3
Peripheral Power Management Set Register (PPMRS)
The PPMRS register provides a simple memory-mapped mechanism to set a given bit in the PPMR
x
registers to disable the clock for a given IPS module without the need to perform a read-modify-write on
the PPMR. The data value on a register write causes the corresponding bit in the PPMR
x
register to be set.
A data value of 64 to 127 provides a global set function, forcing the entire contents of the PPMR
x
to be
set, disabling all IPS module clocks. Reads of this register return all zeroes. See
and
for the PPMRS definition.
7
ENBSTOP
Enable low-power stop mode.
0 Low-power stop mode disabled
1 Low-power stop mode enabled. After the core is stopped and the signal to enter stop mode is asserted,
processor clocks can be disabled.
6–4
XLPM_IPL
[2:0]
Exit low-power mode interrupt priority level. This field defines the interrupt priority level needed to exit the
low-power mode.Refer to
3–0
—
Reserved, should be cleared.
Table 9-5. XLPM_IPL Settings
XLPM_IPL[2:0]
Interrupts Level Needed to Exit Low-Power Mode
000
Any interrupt request exits low-power mode
001
Interrupt request levels 2–7 exit low-power mode
010
Interrupt request levels 3–7 exit low-power mode
011
Interrupt request levels 4–7 exit low-power mode
100
Interrupt request levels 5–7 exit low-power mode
101
Interrupt request levels 6–7 exit low-power mode
11x
Interrupt request level 7 exits low-power mode
IPSBAR
Offset:
0x00_0021 (PPMRS)
Access: write-only
7
6
5
4
3
2
1
0
R
0
W
PPMRS
Reset:
0
0
0
0
0
0
0
0
Figure 9-4. Peripheral Power Management Set Register (PPMRS)
Table 9-4. LPICR Field Description (continued)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
