General Purpose I/O Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
14-11
14.6.5
Pin Assignment Registers
All pin assignment registers are read/write. Refer to
for the different functions assignable to each
pin.
Some signals can be assigned to different pins (see
). However, a signal should not be assigned
to more than one pin at the same time. If a signal is assigned to two or more pins simultaneously, the result
is undefined.
14.6.5.1
Dual Function Pin Assignment Registers
The dual function pin assignment registers allow each pin controlled by each register bit to be configured
for the primary function or the GPIO function. The fields are described in
, which applies to all
dual-function registers.
Table 14-5. CLRn Field Descriptions
Field
Description
CLRnx
Port nx pin data/set data bits.
1 Never returned for reads; no effect for writes
0 Always returned for reads; clears corresponding port nx bit for writes
IPSBAR
Offsets:
0x10_006A (PANPAR)
0x10_0074 (PDDPAR)
0x10_0076 (PGPPAR)
Access: User read/write
7
6
5
4
3
2
1
0
R
P
n
PAR7
P
n
PAR6
P
n
PAR5
P
n
PAR4
P
n
PAR3
P
n
PAR2
P
n
PAR1
P
n
PAR0
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-18. Dual-Function Pin Assignment Registers with Bits 7:0 Implemented (PANPAR, PDDPAR,
PGPPAR)
IPSBAR
Offset: 0x10_0075 (PLDPAR)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
P
n
PAR6
P
n
PAR5
P
n
PAR4
P
n
PAR3
P
n
PAR2
P
n
PAR1
P
n
PAR0
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-19. Port LD Pin Assignment Register (PLDPAR)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
