General Purpose I/O Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
14-12
Freescale Semiconductor
14.6.5.2
Quad-Function Pin Assignment Registers
The quad function pin assignment registers allow each pin controlled by each register bit to be configured
for the primary, alternate 1 (secondary), alternate 2 (tertiary), and GPIO (quaternary) functions. The fields
are described in
, which applies to all quad-function registers.
IPSBAR
Offsets:
0x10_0070 (PTDPAR)
0x10_0073 (PUCPAR)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
P
n
PAR3
P
n
PAR2
P
n
PAR1
P
n
PAR0
W
Reset:
0
0
0
0
0
0
0
0
Figure 14-20. Dual-Function Pin Assignment Registers with Bits 3:0 Implemented (PTDPAR, PUCPAR)
Table 14-6. Dual-Function PnPAR Field Descriptions
Field
Description
PnPARx
PnPARx pin assignment register bits.
1 Pin assumes its primary function
0 Pin assumes its GPIO function
IPSBAR
Offset: 0x10_0068 (PNQPAR)
Access: User read/write
15
14
13
12
11
10
9
8
R
P
n
PAR7
P
n
PAR6
P
n
PAR5
P
n
PAR4
W
Reset
0
0
0
0
0
0
0
0
7
6
5
4
3
2
1
0
R
P
n
PAR3
P
n
PAR2
P
n
PAR1
0
0
W
Reset
0
0
0
0
0
0
0
0
Figure 14-21. Port NQ Pin Assignment Register (PNQPAR)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
