Interrupt Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
15-11
Freescale Semiconductor
15.3.7
Software and Level m IACK Registers (SWIACKn, LmIACKn)
The eight IACK registers can be explicitly addressed via the CPU, or implicitly addressed via a
processor-generated interrupt acknowledge cycle during exception processing. In either case, the interrupt
controller’s actions are very similar.
When a level-
m
IACK arrives in the interrupt controller, the controller examines all the currently-active
level m interrupt requests, determines the highest priority within the level, and then responds with the
unique vector number corresponding to that specific interrupt source. The vector number is supplied as the
data for the byte-sized IACK read cycle. In addition to providing the vector number, the interrupt controller
also loads the level and priority number for the level into the IACKLPR register, where it may be retrieved
later.
This interrupt controller design also supports the concept of a software IACK. A software IACK allows
an interrupt service routine to determine if there are other pending interrupts so that the overhead
associated with interrupt exception processing (including machine state save/restore functions) can be
minimized. In general, the software IACK is performed near the end of an interrupt service routine, and if
there are additional active interrupt sources, the current interrupt service routine (ISR) passes control to
the appropriate service routine, but without taking another interrupt exception.
When the interrupt controller receives a software IACK read, it returns the vector number associated with
the highest level, highest priority unmasked interrupt source for that interrupt controller. The IACKLPR
register is also loaded as the software IACK is performed. If there are no active sources, the interrupt
IPSBAR
Offsets: See
for register offsets (ICRnx)
Access: R/W (Read only for ICRn1-ICRn7)
7
6
5
4
3
2
1
0
R
0
0
IL
IP
W
Reset:
0
0
0
0
0
0
0
0
Note: It is the responsibility of the software to program the ICRnx registers with unique and non-overlapping level
and priority definitions. Failure to program the ICRnx registers in this manner can result in undefined
behavior. If a specific interrupt request is completely unused, the ICRnx value can remain in its reset (and
disabled) state.
Figure 15-9. Interrupt Control Register (ICRnx)
Table 15-13. ICRnx Field Descriptions
Field
Description
7–6
Reserved, must be cleared.
5–3
IL
Interrupt level. Indicates the interrupt level assigned to each interrupt input.
2–0
IP
Interrupt priority. Indicates the interrupt priority for internal modules within the interrupt-level assignment. 0x0
represents the lowest priority and 0x7 represents the highest. For the fixed level interrupt sources, the priority is fixed
at the midpoint for the level, and the IP field always reads as 0x0.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
