Interrupt Controller Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
15-4
if interrupt source 2 is active and acknowledged,
then Vector number = 66
...
if interrupt source 8 is active and acknowledged,
then Vector number = 72
if interrupt source 9 is active and acknowledged,
then Vector number = 73
...
if interrupt source 62 is active and acknowledged,
then Vector number = 126
The net effect is a fixed mapping between the bit position within the source to the actual interrupt vector
number.
If there is no active interrupt source for the given level, a special spurious interrupt vector (vector
number = 24) is returned. It is the responsibility of the service routine to manage this error situation.
This protocol implies the interrupting peripheral is not accessed during the acknowledge cycle because the
interrupt controller completely services the acknowledge. This means the interrupt source must be
explicitly disabled in the interrupt service routine. This design provides unique vector capability for all
interrupt requests, regardless of the complexity of the peripheral device.
15.2
Memory Map
The register programming model for the interrupt controllers is memory-mapped to a 256-byte space. In
the following discussion, there are a number of program-visible registers greater than 32 bits. For these
control fields, the physical register is partitioned into two 32-bit values: a register high (the upper
longword, represented by an appended H) and a register low (the lower longword, represented by an
appended L).
The registers and their locations are defined in
. The register names include the (zero-based)
interrupt controller number
n
, which is useful in devices with multiple controllers. This device has only
one interrupt controller; hence,
n
= 0.
Table 15-2. Interrupt Controller Base Addresses
Interrupt Controller Number
Base Address
INTC0
0xC00
INTC1
0xD00
Global IACK Registers Space
1
1
This address space only contains the L1ACK-L7IACK registers. See
Section 15.3.7, “Software and Level m
IACK Registers (SWIACKn, LmIACKn)
" for more information
0xF00
Table 15-3. Interrupt Controller Memory Map
Address
Register
Width
(bits)
Access
Reset Value
Section/
Page
Interrupt Controller 0
0x00_0C00
Interrupt Pending Register High (IPRH0)
32
R
0x0000_0000
0x00_0C04
Interrupt Pending Register Low (IPRL0)
32
R
0x0000_0000
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from
the
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International
Trade
Commission,
BGA-packaged
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for
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
