Edge Port Modules (EPORTn)
16-4
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
16.4.2
EPORT Data Direction Register (EPDDR)
The EPORT data direction register (EPDDR) controls the direction of each one of the pins individually.
Table 16-3. EPPAR Field Descriptions
Field
Description
15–0
EPPAn
EPORT pin assignment select fields. The read/write EPPAn fields configure EPORT pins for level detection and rising
and/or falling edge detection.
Pins configured as level-sensitive are active-low (logic 0 on the external pin represents a valid interrupt request).
Level-sensitive interrupt inputs are not latched. To guarantee that a level-sensitive interrupt request is acknowledged,
the interrupt source must keep the signal asserted until acknowledged by software. Level sensitivity must be selected
to bring the device out of stop mode with an IRQn interrupt.
Pins configured as edge-triggered are latched and need not remain asserted for interrupt generation. A pin
configured for edge detection can trigger an interrupt regardless of its configuration as input or output.
Interrupt requests generated in the EPORT module can be masked by the interrupt controller module. EPPAR
functionality is independent of the selected pin direction.
Reset clears the EPPAn fields.
00 Pin IRQn level-sensitive
01 Pin IRQn rising edge triggered
10 Pin IRQn falling edge triggered
11 Pin IRQn falling edge and rising edge triggered
IPSBAR
Offset:
0x13_0002 (EPDDR0)
0x14_0002 (EPDDR1)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
EPDD7
EPDD6
EPDD5
EPDD4
EPDD3
EPDD2
EPDD1
EPDD0
W
Reset
0
0
0
0
0
0
0
0
Figure 16-3. EPORT Data Direction Register (EPDDR)
Table 16-4. EPDDR Field Descriptions
Field
Description
7–0
EPDDn
Setting any bit in the EPDDR configures the corresponding pin as an output. Clearing any bit in EPDDR configures
the corresponding pin as an input. Pin direction is independent of the level/edge detection configuration. Reset clears
EPDD7–EPDD0.
To use an EPORT pin as an external interrupt request source, its corresponding bit in EPDDR must be clear.
Software can generate interrupt requests by programming the EPORT data register when the EPDDR selects output.
0 Corresponding EPORT pin configured as input
1 Corresponding EPORT pin configured as output
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
