FlexCAN
30-29
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
4. Initialize FlexCAN interrupt handler.
a) Initialize the interrupt controller registers for any needed interrupts. See
for more information.
b) Set the required mask bits in the IMASK register (for all message buffer interrupts) and the
CANCTRL (for bus off and error interrupts).
5. Clear the CANMCR[HALT] bit. At this point, the FlexCAN attempts to synchronize with the CAN
bus.
30.4.1
Interrupts
There are 18 interrupt sources for the FlexCAN module. An interrupt for each of the 16 MBs. The other
interrupt sources (bus off and error) act in the same manner, and are located in the ERRSTAT register. The
bus off and error interrupt mask bits are located in the CANCTRL register.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
