Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
31-38
Freescale Semiconductor
31.4.2
Real-Time Debug Support
The ColdFire family provides support debugging real-time applications. For these types of embedded
systems, the processor must continue to operate during debug. The foundation of this area of debug support
is that while the processor cannot be halted to allow debugging, the system can generally tolerate the small
intrusions of the BDM inserting instructions into the pipeline with minimal effect on real-time operation.
The debug module provides four types of breakpoints: PC with mask, PC without mask, operand address
range, and data with mask. These breakpoints can be configured into one- or two-level triggers with the
exact trigger response also programmable. The debug module programming model can be written from the
external development system using the debug serial interface or from the processor’s supervisor
programming model using the WDEBUG instruction. Only CSR is readable using the external
development system.
31.4.2.1
Theory of Operation
Breakpoint hardware can be configured through TDR[TCR] to respond to triggers by displaying DDATA,
initiating a processor halt, or generating a debug interrupt. As shown in
, when a breakpoint is
triggered, an indication (CSR[BSTAT]) is provided on the DDATA output port when it is not displaying
captured processor status, operands, or branch addresses.
The breakpoint status is also posted in the CSR. CSR[BSTAT] is cleared by a CSR read when a level-2
breakpoint is triggered or a level-1 breakpoint is triggered and a level-2 breakpoint is not enabled. Status
is also cleared by writing to TDR to disable trigger options.
BDM instructions use the appropriate registers to load and configure breakpoints. As the system operates,
a breakpoint trigger generates the response defined in TDR.
PC breakpoints are treated in a precise manner—exception recognition and processing are initiated before
the excepting instruction executes. All other breakpoint events are recognized on the processor’s local bus,
but are made pending to the processor and sampled like other interrupt conditions. As a result, these
interrupts are imprecise.
In systems that tolerate the processor being halted, a BDM-entry can be used. With TDR[TRC] equals 01,
a breakpoint trigger causes the core to halt (PST = 0xF).
If the processor core cannot be halted, the debug interrupt can be used. With this configuration,
TDR[TRC] equals 10, breakpoint trigger becomes a debug interrupt to the processor, which is treated
Table 31-23. DDATA[3:0]/CSR[BSTAT] Breakpoint Response
DDATA[3:0]
CSR[BSTAT]
1
1
Encodings not shown are reserved for future use.
Breakpoint Status
0000
0000
No breakpoints enabled
0010
0001
Waiting for level-1 breakpoint
0100
0010
Level-1 breakpoint triggered
1010
0101
Waiting for level-2 breakpoint
1100
0110
Level-2 breakpoint triggered
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