Cryptographic Acceleration Unit (CAU)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
5-6
Freescale Semiconductor
Section 5.4.2, “Assembler Equate Values,”
contains a set of assembly constants used in the command
descriptions here. If supported by the assembler, macros can also be created for each instruction. The value
CA
x
should be interpreted as any CAU register (CASR, CAA, CA
n
) and the <ea> field as one of the
supported ColdFire addressing modes {Rn, (An), -(An), (An)+, (d16,An)}. For example, the instruction to
add the value from the core register D1 to the CAU register CA0 is:
c
p0ld.l %d1,#ADR+CA0 ; CA0=CA0+d1
5.3.3.1
Coprocessor No Operation (
CNOP
)
cp0ld.l #CNOP
The
CNOP
command is the coprocessor no-op defined by the ColdFire coprocessor definition for
synchronization. It is not actually issued to the coprocessor from the core.
5.3.3.2
Load Register (
LDR
)
cp0ld.l <ea>,#LDR+CAx
The
LDR
command loads CAx with the source data specified by <ea>.
5.3.3.3
Store Register (
STR
)
cp0st.l <ea>,#STR+CAx
The
STR
command stores the value from CAx to the destination specified by <ea>.
5.3.3.4
Add to Register (
ADR
)
cp0ld.l <ea>,#ADR+CAx
The
ADR
command adds the source operand specified by <ea> to CAx and stores the result in CAx.
5.3.3.5
Reverse and Add to Register (
RADR
)
cp0ld.l <ea>,#RADR+CAx
The
RADR
command performs a byte reverse on the source operand specified by <ea>, adds that value to
CAx, and stores the result in CAx.
shows an example.
5.3.3.6
Add Register to Accumulator (
ADRA
)
cp0ld.l #ADRA+CAx
The
ADRA
command adds CAx to CAA and stores the result in CAA.
5.3.3.7
Exclusive Or (
XOR
)
cp0ld.l <ea>,#XOR+CAx
Table 5-6.
RADR
Command Example
Operand
CAx Before
CAx After
0x0102_0304
0xA0B0_C0D0
0xA4B3_C2D1
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
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sale
in
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
