Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
5-6
Freescale Semiconductor
Preliminary
5.2.2.2
RTC Status and Control Register (CRP_RTCSC)
The CRP_RTCSC register contains:
•
RTC counter enable
•
RTC interrupt enable
•
RTC interrupt flag
•
RTC counter roll over interrupt flag
•
RTC clock source select
•
RTC compare value
•
API enable
•
API interrupt enable
•
API interrupt flag
•
API compare value
TRIM32IRC[0:7]
1
Trim Value for 32 kHz IRC. The TRIM32IRC bits control the 32 kHz IRC internal reference clock frequency
by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e. bit 6 adjusts
twice as much as bit 7). Increasing the binary value decreases the period and decreasing the value
increases the period.
Note: A trim value of 0xff is reserved and is not a valid trim value.
TRIMIRC[0:7]
Trim Value for 16 MHz IRC. The TRIMIRC bits control the 16 MHz IRC internal reference clock frequency
by controlling the internal reference clock period. The bits’ effect are binary weighted (i.e. bit 6 adjusts
twice as much as bit 7). Increasing the binary value decreases the period and decreasing the value
increases the period.
Bits 0–2 control the bandgap voltage trim.
Note: Do not change bits 0–2 to any values other than the Factory Trim values or the default reset values.
Bits 3–7 control the IRC current reference.
1
See
Chapter 22, “Flash Array and Control
” for factory trim value locations in memory.
Offset:
CR 0x0010
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
CNTEN RTCIE
RTCF ROVRF
RTCVAL
W
w1c
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
APIEN APIIE
APIF
CLKSEL
ROVREN
APIVAL
W
w1c
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
These bits are only reset by power-on, VDD15 LVI, VDD33 LVI, and VDDSYN LVI, VDD5 low LVI, and VDD5
LVI.
Figure 5-3. RTC Status and Control Register (CRP_RTCSC)
Table 5-2. CRP_CLKSRC Field Descriptions (continued)
Field
Description
