System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
6-24
Freescale Semiconductor
Preliminary
6.3.2.13.2
Pad Configuration Registers 16–143 (SIU_PCR16–SIU_PCR143)
The SIU_PCR16 to SIU_PCR143 registers control the pin function, direction, and static electrical
attributes of the Port B (PB0-PB15), Port C (PC0-PC15), Port D (PD0-PD15), Port E (PE0-PE15), Port F
(PF0-PF150), Port G (PG0-PG15), Port H (PH0-PH15), and Port J (PJ0-PJ15) pins. For each pin,
lists the signals that are available as the PA settings for Function1, Function2 and Function3.
6.3.2.13.3
Pad Configuration Registers 144–145 (SIU_PCR144–SIU_PCR145)
The SIU_PCR144 and SIU_PCR145 registers control the pin function and static electrical attributes of the
Port K pins PK0 and PK1 (input only). For each pin,
lists the signals available as the PA settings
for Function1, Function2 and Function3.
6.3.2.14
GPIO Pin Data Output Registers (SIU_GPDO16_19–SIU_GPDO140_143)
The SIU_GPDO16_19 register definition is in
x
_
x
registers follow the
same pattern where four GPDO bits are placed in a 32-bit word, with one bit per byte. Each of the 128
PDO bits corresponds to a port pin in the order given in
. Gaps exist in this memory space where
the pin is not available in the package.
NOTE
On MPC5510, the Port A and Port K pins are only general-purpose inputs.
Therefore, there are no output data registers associated with these pins.
The SIU_GPDO
x
_
x
registers are written to by software to drive data out on the external GPIO pin. Each
byte of a register drives a single external GPIO pin, which allows the pin state to be controlled
independently from other GPIO pins. Writes to the SIU_GPDO
x
_
x
registers do not affect pin states if the
pins are configured as inputs or as non-GPIO function by the associated pad configuration registers. The
Offset:
S0x0060–S0x015F
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
PA
OBE
IBE
0
0
ODE
HYS
SRC
WPE
WPS
W
Reset
0
0
0
0
0
0
0
U
0
0
0
0
0
0
0
1
The reset value is 1 for PCR50 (BOOTCFG), 0 for all other PCRs in this range
Figure 6-15. Port B to Port K Pad Configuration Registers (SIU_PCR16 - SIU_PCR145)
Offset:
S0x0160–S0x0163
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
PA
0
IBE
0
0
ODE
HYS
0
0
WPE
WPS
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
The IBE bit should be 0 when analog input function is selected.
Figure 6-16. Port K Pad Configuration Registers (SIU_PCR144–SIU_PCR145)
