Reset
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
7-3
Preliminary
7.3.2
Reset Sources
7.3.2.1
Power-on Reset (POR)
The internal power-on reset signal is asserted when the voltage on the 5 V VDDA supply is below defined
values. See the
MPC5510 Microcontroller Family Data Sheet
Section 7.3.2.2, “Low-Voltage Inhibit
7.3.2.2
Low-Voltage Inhibit (LVI) Resets
The internal LVI reset signals are asserted when the voltage on the corresponding supply is below defined
values. The following are the LVI resets:
•
LVI15S: LVI on 1.5 V supply
•
LVI33S: LVI on 3.3 V supply (used for 3.3 V power to internal I/O pad logic)
•
LVI33SYNS: LVI on 3.3 V supply (used for VDDSYN)
•
LVI5S: LVI on 5 V VDDA supply (nominal trip point V
LV5A
)
•
LVI5CS: LVI on 5 V VDDA supply (nominal trip point 4.0 V used during crank operation)
7.3.2.3
External Reset
When the reset controller detects assertion of the RESET pin, the internal reset signal is asserted. The
SIU_RSR[ERS] bit is set, and all other reset status bits in the SIU_RSR are cleared.
7.3.2.4
Loss-of-Lock Reset
A loss-of-lock reset occurs when the PLL loses lock and the loss-of-lock reset enable (LOLRE) bit in the
PLL enhanced synthesizer control register 2 (ESYNCR2) is set. The internal reset signal and RESET pin
are asserted. The SIU_RSR[LLRS] bit is set, and all other reset status bits in the SIU_RSR are cleared.
7.3.2.5
Loss-of-Clock Reset
A loss-of-clock reset occurs when a failure is detected in either the reference clock signal or PLL output
when the PLL is enabled. The internal reset signal and RESET pin are asserted. The SIU_RSR[LCRS] bit
is set, and all other reset status bits in the SIU_RSR are cleared.
7.3.2.6
Watchdog Timer
A watchdog timer reset occurs when the miscellaneous controller module (MCM) SWT watchdog timer
is enabled and is not serviced properly. The affect of a watchdog timer reset is the same for the reset
controller. The internal reset signal and RESET pin are asserted. The SIU_RSR[WTRS] bit is set, and all
other reset status bits in the SIU_RSR are cleared.
7.3.2.7
Checkstop Reset
When the Z1 or Z0 core enters a checkstop state, and the checkstop reset is enabled (SIU_SRCR[CRE0]
bit for Z1 and the SIU_SRCR[CRE1] bit for Z0), a checkstop reset occurs. The internal reset signal and
