Interrupts
MPC5510 Microcontroller Family Reference Manual, Rev. 1
8-2
Freescale Semiconductor
Preliminary
request. The interrupt exception handler reads the INTC_IACKR to learn the vector of the source of the
interrupt request. In hardware vector mode, the interrupt exception handler is unique to the interrupt
request source’s vector.
8.2
Interrupt Vectors
The core interrupt vectors are located on a 4 KB boundary in the memory map, with the hardware interrupt
vectors located 2 KB above the core interrupt vectors (see
).
Figure 8-1. MPC5510 Interrupt Vector Memory Map
8.2.1
Core Interrupts
Table 8-1. MPC5510 Core Interrupt Vector Memory Map
Core Interrupt Type
IVOR #
1
VPR
Offset
Enables
2
State
Saved In
Examples
Critical Input
IVOR 0
0x000
CE
CSRR[0:1] Non maskable interrupt (pins PD[10],
PD[11])
Machine Check
IVOR 1
0x010
ME
CSRR[0:1] ISI, ITLB error on first instruction of
exception handler
Data Storage
IVOR 2
0x020
—
SRR[0:1]
Incorrect privilege mode for R/W access
Instruction Storage
IVOR 3
0x030
—
SRR[0:1]
Incorrect privilege mode for instruction
External Input
3
IVOR 4
0x040
EE, src
SRR[0:1]
Peripherals, IRQ pins, software
Alignment
IVOR 5
0x050
—
SRR[0:1]
Load or store operand not word aligned
Program
IVOR 6
0x060
—
SRR[0:1]
Illegal instruction, trap
Floating Point Unavailable
4
IVOR 7
0x070
—
SRR[0:1]
FP instruction attempt with MSR[FP]=0
System Call
IVOR 8
0x080
—
SRR[0:1]
System call, “sc”, instruction
Decrementer
IVOR 10
0x0A0
EE, DIE
SRR[0:1]
Decrementer timeout
Fixed Interval Timer
IVOR 11
0x0B0
EE, FIE
SRR[0:1]
Fixed-interval timer timeout
Watchdog Timer
IVOR 12
0x0C0
CE, WIE
CSRR[0:1] Watchdog timeout when ENW=1, WIS=0
INTC
Hardware
IVPR + 2 KB
IVPR
(4 KB boundary)
Core
Interrupt
Vectors
Vector Mode
Interrupt
Vectors