MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
1-1
Preliminary
Chapter 1
Overview
1.1
Introduction
The MPC5510 is a family of next generation microcontrollers built on the Power Architecture
™
embedded
category. This document describes the proposed features of the family and potential options available
within the planned family members, and highlights the important electrical and physical characteristics of
the device. This is a preliminary document for a product family that is still in development. Its purpose is
to communicate information on the intended features of the family members. Information contained within
this document is subject to change without notice.
NOTE: Bit and Field Numbering Conventions
In this reference manual, register bits and fields are generally numbered
according to the convention used in the Power Architecture standard
(MSB=0); however, in some instances the bit/field numbering may appear
to be reversed. This is due to the fact that some of the modules were
designed for use on devices that use either the MSB=0 numbering
convention or the alternative convention (LSB=0), for example, the HC12
and 68K families, and simple reversing of bit/field numbers is not possible.
In the Nexus standard, register bits are numbered according to the
alternative convention (LSB=0). As the CPU core on the MPC5510 family
cannot access Nexus registers directly (they are accessed thought external
tools), register bits are numbered according to the LSB=0 convention in the
Nexus chapter.
The MPC5510 family of 32-bit microcontrollers is Freescale Semiconductor’s latest achievement in
integrated automotive application controllers. It belongs to an expanding family of automotive-focused
products designed to address the next wave of central body and gateway applications within the vehicle.
Freescale’s advanced and cost-efficient host processor core of the MPC5510 automotive controller family
is compatible with the Power Architecture Book E architecture. It operates at speeds of up to 80 MHz and
offers high-performance processing optimized for low-power consumption. It capitalizes on the available
development infrastructure of the current Power Architecture devices and will be supported with software
drivers, operating systems, and configuration code to assist with user implementations.
The MPC5510 platform has a single level of memory hierarchy and can support up to 80 KB of on-chip
static random access memory (SRAM) and 1.5 MB of internal flash memory. Refer to
specific memory and feature sets of the proposed roadmap product members.
