Peripheral Bridge (AIPS-lite)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
14-2
Freescale Semiconductor
Preliminary
Figure 14-1. AIPS-lite Block Diagram
14.1.3
Features
The AIPS-lite has these major features:
•
AIPS-lite supports the IPS slave interface signals. This interface is meant for slave peripherals
only.
•
AIPS-lite supports 32-bit IPS peripherals. (Byte, halfword, and word reads and write are supported
to each.)
•
Read and write accesses of 32 bits or less require two clocks, provided they do not cross a 32-bit
boundary.
— Read and write accesses that cross a 32-bit boundary are not supported.
•
The peripherals connected to the AIPS-lite may be configured in groups to run at less than the
system clock frequency. See
Section 3.4.5, “Peripheral Clock Dividers
,” for a description of these groups.
14.1.4
Modes of Operation
The AIPS-lite has only one operating mode.
14.2
External Signal Description
The AIPS-lite has no external signals.
14.3
Memory Map and Registers
The AIPS-lite does not contain any user-programmable registers.
14.4
Functional Description
The AIPS-lite serves as an interface between an AHB 2.v6 system bus and the peripheral interface bus. It
functions as a protocol translator.
On-Chip Peripherals
32
AMBA AHB
AMBA AHB
AMBA AHB
MUX Logic
AXBS
32
32
32
Peripheral
Bridge
(AIPS-lite)
