Crossbar Switch (XBAR)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
15-5
Preliminary
miscellaneous user defined control register as described in
Section 16.2.2.4, “Miscellaneous User-Defined
15.4.3.1
Arbitration During Undefined Length Bursts
The XBAR is explicitly configured to arbitrate after each transfer in an underfined-length burst.
15.4.3.2
Round-Robin Priority Operation
When operating in round-robin mode, each master is assigned a relative priority based on the master
number. This relative priority is compared to the ID of the last master to perform a transfer on the slave
bus. The highest priority requesting master will become owner of the slave bus at the next transfer
boundary (accounting for locked and burst transfers). Priority is based on how far ahead the ID of the
requesting master is to the ID of the last master (ID is defined by master port number).
Once granted access to a slave port, a master may perform as many transfers as desired to that port until
another master makes a request to the same slave port. The next master in line will be granted access to
the slave port at the termination of the current bus access, or on the next clock cycle if the current master
has no pending access request.
As an example of arbitration in round-robin mode, assume the XBAR is implemented with master ports 0,
1, 4, and 5. If the last master of the slave port was master 1, and masters 0, 4, and 5 make simultaneous
requests, they will be serviced in the order 4, 5, and then 0.
Parking may still be used in a round-robin mode, but will not affect the round-robin pointer unless the
parked master performs a transfer. Handoff will occur to the next master in line after one cycle of
arbitration.
Each master port has a high priority request input signal. If a master port's high priority request input is
enabled for a slave port programmed for round-robin mode, that master can force the slave port into fixed
priority mode by asserting its high priority request input while making a request to that particular slave
port. While that (or any enabled) master’s high priority request input is asserted while making an access
attempt to that particular slave port, the slave port will remain in fixed priority mode. After that (or any
enabled) master’s high priority request input is negated, or the master no longer attempts to make accesses
to that particular slave port, the slave port will revert back to round-robin priority mode and the pointer
will be set on the last master to access the slave port.
NOTE
When either the e200z1 or e200z0 request an external or critical interrupt,
or for certain configurations of an active eDMA transfer control descriptor,
a high priority access will be requested that puts the requesting master at the
front of the queue. The ability to enable the high-priority request from the
processors is programmable. This feature is enabled via the assertion of the
appropriate HID1 control bits in the e200 core.
