Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
16-4
Freescale Semiconductor
Preliminary
16.2.2
Register Descriptions
This section lists the MCM registers in address order and describes the registers and their bit fields.
Attempted accesses to reserved addresses result in an error termination; however, attempted writes to
read-only registers are ignored and do not terminate with an error.
NOTE
Unless noted otherwise, writes to the programming model must match the
size of the register, e.g., an
n
-bit register only supports
n
-bit writes, etc.
Attempted writes of a different size than the register width produce an error
termination of the bus cycle and no change to the targeted register.
16.2.2.1
Software Watchdog Timer Control Register (SWTCR)
The software watchdog timer (SWT) prevents system lockup if the software becomes trapped in a loop
with no controlled exit or if a bus transaction becomes hung. The software watchdog timer can be enabled
or disabled through the SWTCR[SWE]. The SWT operates in a separate, asynchronous clock domain and
contains clock domain synchronizers as the communication mechanism between the system clock domain
and the software watchdog timer domain. If enabled, the watchdog timer requires the periodic execution
of a software watchdog servicing sequence. If this periodic servicing action does not occur, the timer
expires, resulting in a watchdog timer interrupt or a hardware reset, as programmed in the
SWTCR[SWRI].
There are three user-defined responses to a time-out:
•
The SWTCR[SWRI] can specify the assertion of a watchdog timer interrupt.
•
The SWTCR[SWRI] can specify the immediate assertion of a system reset.
•
The SWTCR[SWRI] can specify a sequence of responses. Upon the first time-out, the watchdog
timer interrupt is asserted. If the watchdog timer interrupt flag is not cleared before a second
time-out occurs
,
the watchdog timer asserts the system reset signal in response to the second
time-out. This configuration supports a more graceful response to watchdog time-outs: first
attempting an interrupt to notify the system, if that fails, generating a system reset.
In addition to these three modes of operation, the watchdog timer also supports a windowed mode of
operation. In this mode, the time-out period is divided into four equal segments and the servicing of the
watchdog timer must occur during the last segment, i.e., during the last 25% of the time-out period. If the
watchdog timer is serviced anytime in the first 75% of the time-out period, an immediate system reset
occurs.
Throughout this section, there are many references to the generation of a system reset. The MCM’s
behavior during this process is detailed below. When the watchdog timer expires and SWTCR[SWRI] is
programmed for a reset (either as the initial or secondary response), the MCM generates a watchdog timer
reset output signal, which is driven to the SIU and will cause a system reset.
The watchdog timer logic also sends an interrupt request to the device’s interrupt controller.
