Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
16-5
Preliminary
To prevent the watchdog timer from interrupting or resetting, the SWTSR must be serviced by performing
the following sequence:
1. Write 0x55 to the SWTSR.
2. Write 0xAA to the SWTSR.
Both writes must occur in this order before the time-out, but any number of instructions can be executed
between the two writes. This definition allows interrupts and exceptions to occur, if necessary, between
the two writes. The timer value is constantly compared with the time-out period specified by
SWTCR[SWT].
NOTE
Any write to the SWTCR resets the watchdog timer.
There is also a read-only control flag included in the SWTCR to prevent accidental updates to this control
register from changing the desired system configuration.
If the second write occurs at the exact same cycle as the time-out condition is reached, the clear takes
precedence and the time-out response suppressed.
The SWTCR controls the software watchdog timer, time-out periods, and time-out response. The register
can be read or written at any time. At system reset, the software watchdog timer is enabled. See
for the software watchdog timer control register definition.
Offset: MCM_BAS 0x0016
Access: User read/write
0
1
2
3
4
5
6
1
1
Bit 6 is reserved and must never be set.
7
8
9
10
11
12
13
14
15
R
RO
0
0
0
0
0
0
SW
RWH
SWE
SWRI
SWT
W
Reset
2
2
The SWTCR default reset values may be modified during BAM execution. Please reference the BAM section for more details.
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
1
Figure 16-1. Software Watchdog Timer Control (SWTCR) Register
Table 16-3. SWTCR Field Descriptions
Field
Description
RO
Read-Only.
0 SWTCR can be read or written.
1 SWTCR can be read only. A system reset is required before this register can again be written. The setting of
this bit is intended to prevent accidental writes of the SWTCR from changing the defined system watchdog
configuration.
bits 1–6
Reserved.
Note: Reserved bit 6 must never be set.
SWRWH
Software Watchdog Run While Halted.
0 SWT stops counting if the processor core is halted.
1 SWT continues to count even while the processor core is halted.
