Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
16-11
Preliminary
NOTE
If an attempt to force a non-correctable inversion (by asserting
EEGR[FRCNCI] or EEGR[FRC1NCI]) and EEGR[ERRBIT] equals 64,
then no data inversion will be generated.
The only allowable values for the 2 control bit enables {FRCNCI, FR1NCI}
are {0,0}, {1,0} and {0,1}. All other values result in undefined behavior.
Table 16-8. EEGR Field Descriptions
Field
Description
bits 0–5
Reserved.
FRCNCI
Force RAM Continuous Noncorrectable Data Inversions. The assertion of this bit forces the RAM controller to
create 2-bit data inversions, as defined by the bit position specified in ERRBIT and the overall odd parity bit,
continuously on every write operation.
After this bit has been enabled to generate another continuous noncorrectable data inversion, it must be cleared
before being set again to properly re-enable the error generation logic.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
0 No RAM continuous 2-bit data inversions are generated.
1 2-bit data inversions in the RAM are continuously generated.
FR1NC
Force RAM One Noncorrectable Data Inversions. The assertion of this bit forces the RAM controller to create one
2-bit data inversion, as defined by the bit position specified in ERRBIT and the overall odd parity bit, on the first
write operation after this bit is set.
The normal ECC generation takes place in the RAM controller, but then the polarity of the bit position defined by
ERRBIT and the overall odd parity bit are inverted to introduce a 2-bit ECC error in the RAM.
After this bit has been enabled to generate a single 2-bit error, it must be cleared before being set again to
properly re-enable the error generation logic.
0 No RAM single 2-bit data inversions are generated.
1 One 2-bit data inversion in the RAM is generated.
bit 8
Reserved.
ERRBIT
Error Bit Position. The vector defines the bit position, which is complemented to create the data inversion on the
write operation. For the creation of 2-bit data inversions, the bit specified by this field plus the odd parity bit of the
ECC code are inverted.
The RAM controller follows a vector bit ordering scheme where LSB=0. Errors in the ECC syndrome bits can be
generated by setting this field to a value greater than the RAM width. For example, consider a 32-bit RAM
implementation.
The 32-bit ECC approach requires seven code bits for a 32-bit word. For RAM data width of 32 bits, the actual
SRAM (32b data + 7b for ECC= 39 bits. The following association between the ERRBIT field and the corrupted
memory bit is defined:
if ERRBIT = 0, then RAM[0] is inverted
if ERRBIT = 1, then RAM[1] is inverted
...
if ERRBIT = 31, then RAM[31] is inverted
if ERRBIT = 64,then ECC Parity[0] is inverted
if ERRBIT = 65,then ECC Parity[1] is inverted
...
if ERRBIT = 70,then ECC Parity[6] is inverted
Note: For ERRBIT values of 32 to 63 and greater than 70, no bit position is inverted.
