Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
23-19
Preliminary
23.3.2.5
DSPI DMA/Interrupt Request Select and Enable Register (DSPI_RSER)
The DSPI_RSER serves two purposes. It enables flag bits in the DSPI_SR to generate DMA requests or
interrupt requests. The DSPI_RSER also selects the type of request to be generated. See the individual bit
descriptions for information on the types of requests the bits support.
NOTE
The user must not write to the DSPI_RSER while the DSPI is running.
bit 7–11
Reserved.
RFOF
Receive FIFO Overflow Flag. Indicates that an overflow condition in the RX FIFO has occurred. The bit is set
when the RX FIFO and shift register are full and a transfer is initiated. The bit is cleared by writing 1 to it.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
bit 13
Reserved.
RFDF
Receive FIFO Drain Flag. Indicates that the RX FIFO can be drained. Provides a method for the DSPI to
request that entries be removed from the RX FIFO. The bit is set while the RX FIFO is not empty. The RFDF
bit can be cleared by writing 1 to it or by an acknowledgement from the eDMA controller when the RX FIFO is
empty.
0 RX FIFO is empty
1 RX FIFO is not empty
Note: In the interrupt service routine, RFDF must be cleared only after the DSPI_POPR register is read.
bit 15
Reserved.
TXCTR
TX FIFO Counter. Indicates the number of valid entries in the TX FIFO. The TXCTR is incremented every time
the DSPI _PUSHR is written. The TXCTR is decremented every time an SPI command is executed and the
SPI data is transferred to the shift register.
TXNXT
PTR
Transmit Next Pointer. Indicates which TX FIFO entry will be transmitted during the next transfer. The
TXNXTPTR field is updated every time SPI data is transferred from the TX FIFO to the shift register. See
Section 23.4.3.4, “Transmit First-In First-Out (TX FIFO) Buffering Mechanism
,” for more details.
RXCTR
RX FIFO Counter. Indicates the number of entries in the RX FIFO. The RXCTR is decremented every time the
DSPI_POPR is read. The RXCTR is incremented after the last incoming databit is sampled, but before the
tASC delay starts. Refer to
Section 23.4.8.1, “Classic SPI Transfer Format (CPHA = 0)
,” for details.
POPNXTPTR Pop Next Pointer. Contains a pointer to the RX FIFO entry that will be returned when the DSPI_POPR is read.
The POPNXTPTR is updated when the DSPI_POPR is read. See
Section 23.4.3.5, “Receive First-In First-Out
,” for more details.
Table 23-5. DSPI_SR Field Descriptions (continued)
Field
Description
