Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-48
Freescale Semiconductor
Preliminary
In the SPI and DSI configurations, the DSPI provides the option of keeping the PCS signals asserted
between frames. See
Section 23.4.8.5, “Continuous Selection Format
23.4.8.1
Classic SPI Transfer Format (CPHA = 0)
is used to communicate with peripheral SPI slave devices
where the first data bit is available on the first clock edge. In this format, the master and slave sample their
SIN
x
pins on the odd-numbered SCK
x
edges and change the data on their SOUT
x
pins on the
even-numbered SCK
x
edges.
Figure 23-30. DSPI Transfer Timing Diagram (MTFE = 0, CPHA = 0, FMSZ = 8)
The master initiates the transfer by placing its first data bit on the SOUT
x
pin and asserting the appropriate
peripheral chip select signals to the slave device. The slave responds by placing its first data bit on its
SOUT
x
pin. After the
t
CSC
delay has elapsed, the master outputs the first edge of SCK
x
. This is the edge
used by the master and slave devices to sample the first input data bit on their serial data input signals. At
the second edge of the SCK
x
the master and slave devices place their second data bit on their serial data
output signals. For the rest of the frame the master and the slave sample their SIN
x
pins on the
odd-numbered clock edges and changes the data on their SOUT
x
pins on the even-numbered clock edges.
After the last clock edge occurs a delay of t
ASC
is inserted before the master negates the PCS signals. A
delay of t
DT
is inserted before a new frame transfer can be initiated by the master.
For the CPHA =0 condition of the master, TCF and EOQF are set and the RXCTR counter is updated at
the next to last serial clock edge of the frame (edge 15) of
For the CPHA=0 condition of the slave, TCF is set and the RXCTR counter is updated at the last serial
clock edge of the frame (edge 16) of
.
SCK
(CPOL = 0)
PCSx/SS
t
ASC
SCK
(CPOL = 1)
Master & Slave
Sample
Master SOUT/
Slave SIN
Master SIN/
Slave SOUT
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
MSB
LSB
t
DT
t
CSC
t
CSC
MSB First (LSBFE = 0):
LSB First (LSBFE = 1):
t
CSC
= PCS to SCK delay.
t
ASC
= After SCK delay.
t
DT
= Delay after transfer (minimum CS idle time).
Master (CPHA = 0): TCF and EOQF are set and RXCTR counter
is updated at next to last SCK edge of frame (edge 15)
Slave (CPHA = 0): TCF is set and RXCTR counter is updated at
last SCK edge of frame (edge 16)
1
2
3
4
5
6
7
8
9
10 11 12 13 14
16
15
