Enhanced Serial Communication Interface (eSCI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
24-7
Preliminary
24.3.2.3
eSCI Data Register (ESCIx_DR)
NOTES
ESCI
x
_DR should not be used in LIN mode, writes to this register are
blocked in LIN mode (ESCIx_LCR[LIN] = 1).
BESM13 Bit Error Sample Mode, Bit 13. Determines when to sample the incoming bit to detect a bit error. (This is only relevant
when FBR is set.)
0 Sample at RT clock 9
1 Sample at RT clock 13 (see
Section 24.4.4.3, “Data Sampling
SBSTP
SCI Bit Error Stop. Stops the SCI when a bit error is asserted. This allows to stop driving the LIN bus quickly after a
bit error has been detected.
0 Byte is completely transmitted
1 Byte is partially transmitted
bit 10
Reserved.
PMSK
Parity Mask. The PMSK bit forces bit 7 in the Data Register to 0 on reads. This can be used to mask the parity bit in
applications which use 7 data bits and 1 parity bit.
ORIE
Overrun Error Interrupt Enable. Generates an interrupt, when a frame error is detected.
NFIE
Noise Flag Interrupt Enable. Generates an interrupt, when noise flag is set.
FEIE
Frame Error Interrupt Enable. Generates an interrupt when a frame error is detected.
PFIE
Parity Flag Interrupt Enable. Generates an interrupt when parity flag is set.
Offset: Base + 0x0006
Access: Read/Write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
R8
T8
0
0
0
0
0
0
R7
R6
R5
R4
R3
R2
R1
R0
W
T7
T6
T5
T4
T3
T2
T1
T0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 24-4. eSCI Data Register (ESCIx_DR)
Table 24-4. ESCIx_DR Field Description
Field
Description
R8
Received Bit 8. R8 is the ninth data bit received when the eSCI is configured for 9-bit data format (M = 1).
T8
Transmit Bit 8. T8 is the ninth data bit transmitted when the eSCI is configured for 9-bit data format (M = 1).
Note: If the value of T8 is the same as in the previous transmission, T8 does not have to be rewritten. The same
value is transmitted until T8 is rewritten.
bits 2–7
Reserved.
R7–R0
T7–T0
Received Bits/Transmit Bits 7–0 for 9-bit or 8-bit Formats. Bits 7–0 from SCI communication may be read from
ESCIx_DR[8–15] (provided that SCI communication was successful). Writing to ESCIx_DR [8–15] provides bits 7–0
for SCI transmission.
Table 24-3. ESCIx_CR2 Field Description (continued)
Field
Description