Enhanced Modular I/O Subsystem (eMIOS200)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
26-42
Freescale Semiconductor
Preliminary
26.5.1.2
Input Programmable Filter (IPF)
The IPF ensures that only valid input pin transitions are received by the unified channel edge detector. A
block diagram of the IPF is shown in
.
The IPF is a 5-bit programmable up counter that is incremented by the selected clock source, according to
bits IF in EMIOS_CCR[n] register.
Figure 26-39. lnput Programmable Filter Submodule Diagram
The input signal is synchronized by system clock. When a state change occurs in this signal, the 5-bit
counter starts counting up. As long as the new state is stable on the pin, the counter remains incrementing.
If a counter overflow occurs, the new pin value is validated. In this case, it is transmitted as a pulse edge
to the edge detector. If the opposite edge appears on the pin before validation (overflow), the counter is
reset. At the next pin transition, the counter starts counting again. Any pulse that is shorter than a full range
of the masked counter is regarded as a glitch and it is not passed on to the edge detector.
a timing diagram of the input filter.
Figure 26-40. Input Programmable Filter Example
26.5.1.3
Clock Prescaler (CP)
The CP divides the GCP output signal to generate a clock enable for the internal counter of the unified
channels. It is a programmable 2-bit down counter. The GCP output signal is prescaled by the value
defined in the UCPRE bits in EMIOS_CCR[n] register. The output is clocked every time the counter
reaches zero. Counting is enabled by setting the UCPREN bit in the EMIOS_CCR[n]. The counter can be
stopped at any time by clearing this bit, thereby stopping the internal counter in the unified channel.
Synchronizer
IF3
clk
IF2
IF1
IF0
5-bit Up Counter
FCK
Prescaled Clock
EMIOSI
Clock
ipg_clk
Filter Out
Selected Clock
5-bit Counter
Filter Out
EMIOSI
Time
IF[3:0] = 0010
