External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-12
Freescale Semiconductor
Preliminary
29.3.2.5
EBI Bus Monitor Control Register (EBI_BMCR)
The EBI_BMCR controls the timeout period of the bus monitor and whether it is enabled or disabled.
TEAF
Transfer Error Acknowledge Flag. Set if the cycle was terminated by an externally generated TEA signal.
0 No error.
1 External TEA occurred.
This bit can be cleared by writing a 1 to it.
BMTF
Bus Monitor Timeout Flag. Set if the cycle was terminated by a bus monitor timeout.
0 No error.
1 Bus monitor timeout occurred.
This bit can be cleared by writing a 1 to it.
Offset: 0x000C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
BMT
BME
0
0
0
0
0
0
0
W
Reset
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
Figure 29-4. EBI Bus Monitor Control Register (EBI_BMCR)
Table 29-6. EBI_BMCR Field Descriptions
Field
Description
bits 0–15
Reserved.
BMT
Bus Monitor Timing. Defines the timeout period, in eight external bus clock resolution, for the bus monitor. See
Section 29.4.1.4, “Bus Monitor
,” for more details on bus monitor operation.
BME
Bus Monitor Enable. Controls whether the bus monitor is enabled for internal to external bus cycles. The BME
bit is ignored (treated as 0) for chip-select accesses with internal TA (SETA=0).
0 Disable bus monitor.
1 Enable bus monitor (for external TA accesses only).
bits 25–31
Reserved.
Table 29-5. EBI_TESR Field Descriptions (continued)
Field
Description
Timeout Period
2 + (8
BMT)
×
External Bus Clock Frequency
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