External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-22
Freescale Semiconductor
Preliminary
29.4.2
External Bus Operations
The following sections provide a functional description of the external bus, the bus cycles provided for
data transfer operations, bus arbitration, and error conditions.
29.4.2.1
External Clocking
The CLKOUT signal sets the frequency of operation for the bus interface directly. Internally, the MCU
uses a phase-locked loop (PLL) circuit to generate a master clock for all of the MCU circuitry (including
the EBI) that is phase-locked to the CLKOUT signal. In general, all signals for the EBI are specified with
respect to the rising-edge of the CLKOUT signal, and they are guaranteed to be sampled as inputs or
changed as outputs with respect to that edge.
29.4.2.2
Reset
Upon detection of internal reset, the EBI immediately terminates all transactions.
8
0
Word @0x1
(2 AHB
transfers)
00
1000
—
z00
0111
8
1
00
10
1011
0011
—
z00
0111
9
0
Word @0x2
(2 AHB
transfers)
00
1100
—
z00
0011
9
1
10
0011
—
z00
0011
10
0
Word @0x3
(2 AHB
transfers)
11
1110
11
z00
0001
10
1
11
1011
11
z00
z10
0011
0111
1
Misaligned case number, from
2
Port size; 0=32 bits, 1=16 bits.
3
External ADDR pins, not necessarily the address on internal master AHB bus.
4
For address with Z — address bit 29 will increment to next word. For all other
cases, address bit 29 will be unchanged.
5
External WE pins. Note that these pins have negative polarity, opposite of the
internal byte strobes in
6
Treated as 1-byte access.
Table 29-12. Misalignment Cases Supported by a 32-bit EBI (external bus) (continued)
#
1
PS
2
Program Size
and byte offset
ADDR[30:31]
3,4
WE[0:3]
5
